Validating Apparatus For Use With A Pair Of Integrated Circuits

• US 20070226498A1
• Filed: 06/03/2007
• Published: 09/27/2007
• Est. Priority Date: 07/15/1997
• Status: Active Grant

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Lapstun, Paul, Walmsley, Simon
• Granted Patent: US 7,747,541 B2
• Time in Patent Office: Days
• US Class Current: 713/168
• CPC Class Codes: B41J 2/165 Preventing or detecting of nozzle clogging, e.g. cleaning, capping or moistening for nozzles
• CPC Class Codes: B41J 2/175 Ink supply systems ; Circuit parts therefor
• CPC Class Codes: B41J 2/17546 electronically
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: B41J 3/42 Two or more complete typewriters coupled for simultaneous operation
• CPC Class Codes: B41J 3/44 Typewriters or selective printing mechanisms having dual functions or combined with, or coupled to, apparatus performing other functions
• CPC Class Codes: G06Q 30/01 Customer relationship services
• CPC Class Codes: G06Q 30/0185 Product, service or business identity fraud
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/043 of tables, e.g. lookup, substitution or mapping
• CPC Class Codes: H04L 2209/26 Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator
• CPC Class Codes: H04L 9/3242 involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC
• CPC Class Codes: H04L 9/3271 using challenge-response
• CPC Class Codes: H04L 9/50 using hash chains, e.g. blockchains or hash trees
• CPC Class Codes: H04N 1/21 Intermediate information storage H04N1/387, H04N1/41 take precedence ; for control between transmitter and receiver or between image input and image output device H04N1/32358; indexing, editing G11B27/00
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 1/2154 the still video camera incorporating a hardcopy reproducing device, e.g. a printer
• CPC Class Codes: H04N 2101/00 Still video cameras
• CPC Class Codes: H04N 23/00 : Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 : Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

An apparatus is provided for validating a device. The apparatus includes a first integrated circuit which is configured to generate a random number, reference information using the random number and a secret key. A control system is configured to: receive the random number and the reference information from the first integrated circuit, receive validation information from a second integrated circuit positioned on the device whereby the validation information is generated by the second integrated circuit using the random number and the secret key, and compare the reference and validation information received from the integrated circuits to validate the device.

Claims

1. An apparatus for validating a device, the apparatus comprising:

a first integrated circuit which is configured to generate a random number, reference information using the random number and a secret key; and

a control system which is configured to;

receive the random number and the reference information from the first integrated circuit, receive validation information from a second integrated circuit positioned on the device whereby the validation information is generated by the second integrated circuit using the random number and the secret key, and compare the reference and validation information received from the integrated circuits to validate the device.

2. An apparatus as claimed in claim 1, wherein the control system is configured to validate the device if said reference and validation information are of equal value.

3. An apparatus as claimed in claim 1, wherein the reference information is generated by applying a function to the generated random number based upon the secret key.

4. An apparatus as claimed in claim 3, wherein the function is a digital signature function or a one-way function.

5. An apparatus as claimed in claim 1, wherein the validation information is generated by applying a function to the random number based upon the secret key.

6. An apparatus as claimed in claim 5, wherein the function is a digital signature function.

7. An apparatus as claimed in claim 6, wherein the digital signature function is a symmetric cryptographic function.

8. An apparatus as claimed in claim 1, wherein the first integrated circuit is configured to generate a vector of random numbers and is configured select the next consecutive random number in the vector with each successive validation attempt.