SILICON DEVICE ON SI: C-OI AND SGOI AND METHOD OF MANUFACTURE

• US 20070228472A1
• Filed: 06/04/2007
• Published: 10/04/2007
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Gluschenkov, Oleg, Dokumaci, Omer
• Granted Patent: US 8,232,153 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/8086 Thin film JFET's

Abstract

A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Claims

1. A structure, comprising:

shallow trench isolation (STI) in a substrate;

a first material and a second material on the substrate mixed to form a first island and second island at a nFET region and a pFET region, respectively; and

a layer of material on the first island and the second island having a lattice constant different than the first island and the second island, wherein the STI relaxes and facilitates the relaxation of the first island and the second island.

2. The structure of claim 1, wherein the first material is Ge material and the second material is Si:

C or C.

3. The structure of claim 1, wherein a layer of Si material is formed on the first island and the second island.

4. The structure of claim 3, wherein the first island comprises substantially SiGe, the second island comprises substantially Si:

C and the Si layer is a strained layer.

5. The structure of claim 3, wherein the Si material is in a tensile stress on the first island and placed in a compressive stress on the second island.

6. The structure of claim 1, wherein the first material is Ge with a Ge % of approximately less than 25% to the substrate.

7. The structure of claim 1, wherein the first island and the second island have a different relaxed crystal lattice.

8. The structure of claim 1, wherein the STI is a high temperature stable amorphous material.

9. The structure of claim 1, wherein the second material is C with concentrations of greater than 1-2% Si:

C.

10. The structure of claim 1, wherein the layer of material includes an Si epitaxial layer on the first island and the second island, the Si epitaxial layer has a different lattice constant than the first island and the second island such that the Si epitaxial layer will strain tensilely and compressively on the first island and the second island, respectively.

11. The structure of claim 1, wherein the first island has a lattice constant a≧

aSi and the second island has a lattice constant a≦

aSi.

12. The structure of claim 11, wherein the first island is comprised substantially of SiGe and the second island is comprised substantially of Si:

C and an epitaxially layer over the SiGe island and the Si;

C layer is under a tensile stress and a compressive stress, respectively, by virtue of lattice matching to the SiGe and Si;

C.

13. The structure of claim 1, wherein the second island is comprised substantially of Si:

C and the C has a range of about 1-4%.

14. A semiconductor structure, comprising:

a substrate;

a relaxed shallow trench isolation of high temperature stable amorphous material formed in the substrate;

a first island of thermally annealed mixed material formed in the substrate at a pFET region;

a second island of thermally annealed mixed material formed in the substrate at an nFET region; and

a strained Si layer formed on at least one of the first island and the second island.

15. The structure of claim 14, wherein one of:

the first island and the second island is comprised substantially of a mixed material of relaxed SiGe,

the first island and the second island is comprised substantially of a mixed material of relaxed Si;

C, and

the first island is comprised substantially of SiGe and the second island is comprised substantially of Si;

C.

16. The structure of claim 15, wherein the high temperature stable amorphous material is Si which is compressively strained when the mixed material is SiGe and tensilely strained when the mixed material is Si:

C.

17. The structure of claim 15, wherein the high temperature stable amorphous material has a different lattice constant than the first island and the second island.