Semiconductor Chip Comprising A Metal Coating Structure And Associated Production Method

• US 20070228567A1
• Filed: 03/28/2007
• Published: 10/04/2007
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mahler, Joachim, Haimerl, Alfred, Kessler, Angela, Schober, Wolfgang, Bauer, Michael
• Granted Patent: US 7,880,300 B2
• Time in Patent Office: Days
• US Class Current: 257/739
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05562 On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48764 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor chip (1) has a metal coating structure (2) which has on an active upper side (3) of the semiconductor chip (1) at least one lower metal layer (8) with copper or copper alloy, on which a central metal layer (9) with nickel is arranged. The metal coating structure (2) is terminated by an upper metal layer (10) of palladium and/or a precious metal. The central metal layer (9) with nickel and/or nickel phosphide has a rough interface (11) with respect to the plastic package molding compound surrounding the metal coating structure (2).

Claims

1. A semiconductor chip comprising a metal coating structure on the active upper side of the semiconductor chip, the metal coating structure having copper-containing interconnects and contact terminal areas and precious-metal-containing bonding areas on the upper side of the semiconductor chip, and the metal coating structure having a number of metal layers arranged one on top of the other, a copper-containing lower metal layer forming the interconnects and the contact terminal areas, a central metal layer, comprising nickel and/or nickel phosphide, covering the lower metal layer, and upper metal layers, comprising palladium and/or precious metals, covering at least the bonding area regions, and the central metal layer, comprising nickel and/or nickel phosphide, having a rough interface with respect to a plastic package molding compound surrounding the metal coating structure and/or with respect to the upper metal layers.

2. The semiconductor chip according to claim 1, wherein the roughness of the interface of the central metal layer is formed galvanically in a front-end process by variation of the current densities during deposition.

3. The semiconductor chip according to claim 1, wherein the roughness of the interface of the central metal layer is so great that there is great adhesiveness with respect to the plastic package molding compound and the roughness of the interface of the central metal layer is so small that the bondability of the bonding areas is still not impaired.

4. The semiconductor chip according to claim 1, wherein the thickness d_u of the lower copper-containing metal layer of the coating structure is 2 μ

m≦

d_u≦

50 μ

m.

5. The semiconductor chip according to claim 1, wherein the total thickness d_o of the upper metal layers is 0.1 μ

m≦

d_o≦

1.0 μ

m.

6. The semiconductor chip according to claim 1, wherein the average roughness height t_m of the central metal layer is 0.05 μ

m≦

t_m≦

1.00 μ

m.

7. The semiconductor chip according to claim 1, wherein a diffusion-inhibiting metal layer comprising tungsten and/or titanium is arranged between the copper-containing metal layer of the contact terminal areas and the contact areas of the semiconductor chip, which are in connection with the electrodes of semiconductor elements of the semiconductor chip.

8. The semiconductor chip according to claim 1, wherein a metal layer comprising tungsten and/or titanium is arranged as a diffusion barrier between the copper-containing metal layer of the interconnects and the passivation layers of the upper side of the semiconductor chip.

9. The semiconductor chip according to claim 1, wherein the cross sections of the interconnects of the metal coating structure have such dimensions that they are capable of carrying source or emitter currents of power semiconductor chips.

10. The semiconductor chip according to claim 1, characterized in that the metal coating structure covers a proportion of the surface area Δ

F of the active upper side of the semiconductor chip with Δ

F≧

50%.

11. A semiconductor device comprising a semiconductor chip according to claim 1.

12. The semiconductor device according to claim 11, wherein the semiconductor device is a power device.

13. A power semiconductor module comprising a semiconductor chip according to claim 1.

14. A method for producing a number of semiconductor chips comprising a metal coating structure made up of a number of metal layers, the method having the following method steps:

producing a semiconductor wafer having semiconductor chip positions arranged in rows and columns and having semiconductor electrode areas on the active upper sides of the semiconductor chip positions;

applying a passivation layer to the active upper sides, while leaving the semiconductor electrode areas free;

reinforcing the semiconductor electrode areas by coating to form contact areas;

selective galvanic or chemical deposition of a lower metal layer, comprising copper or copper alloy, of a multi-layered metal coating structure while forming interconnects and contact terminal areas to the contact areas and forming bonding area regions;

selective galvanic deposition of a rough nickel coating as a central metal layer on the lower metal layer;

selectively applying a palladium and/or a precious metal layer to the rough nickel coating, at least in the bonding area regions;

separating the semiconductor wafer into individual semiconductor chips.

15. The method according to claim 14, wherein, after the application of the passivation layer and the reinforcement of the semiconductor electrode areas to form contact areas, the entire surface is transformed into an electrically conducting state by physical deposition of an electrically conducting material by means of sputtering or vapor deposition or plasma coating.

16. The method according to claim 14, wherein, after the deposition of an electrically conducting material on the entire surface, the regions of the surface on which no lower copper-containing or copper-alloy-containing metal layer is to be deposited are protected with a photoresist layer.

17. A semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:

copper-containing interconnects and contact terminal areas and precious-metal-containing bonding areas on the active upper side,

a number of metal layers arranged one on top of the other comprising a copper-containing lower metal layer forming the interconnects and the contact terminal areas, a central metal layer, comprising nickel and/or nickel phosphide, covering the lower metal layer, and upper metal layers, comprising palladium and/or precious metals, covering at least the bonding area regions, wherein the central metal layer, comprising nickel and/or nickel phosphide, has a rough interface with respect to a plastic package molding compound surrounding the metal coating structure and/or with respect to the upper metal layers.

18. The semiconductor chip according to claim 17, wherein the roughness of the interface of the central metal layer is formed galvanically in a front-end process by variation of the current densities during deposition.

19. The semiconductor chip according to claim 17, wherein the roughness of the interface of the central metal layer is so great that there is great adhesiveness with respect to the plastic package molding compound and the roughness of the interface of the central metal layer is so small that the bondability of the bonding areas is still not impaired.

20. The semiconductor chip according to claim 17, wherein the thickness d_u of the lower copper-containing metal layer of the coating structure is 2 μ

m≦

d_u≦

50 μ

m.