On-chip comparison and response collection tools and techniques

• US 20070234163A1
• Filed: 02/20/2007
• Published: 10/04/2007
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz
• Granted Patent: US 7,913,137 B2
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Claims

1. A method of testing a plurality of circuits in a testing system, comprising:

at a first input of one of the plurality of circuits, receiving masking data for controlling a masking circuit; and

at a second input of the one of the plurality of circuits, receiving expected test response data for evaluating test responses generated during testing of the one of the plurality of circuits,

the masking data and the expected test response data being received simultaneously at the first and second inputs.

2. The method of claim 1, wherein the test responses are compacted test responses.

3. The method of claim 1, further comprising:

loading the test responses into a multiple-input shift register (MISR);

producing one or more compactor signatures in the MISR; and

storing the one or more compactor signatures in one or more computer-readable media.

4. The method of claim 3, further comprising:

generating a list of candidate fault locations according to the one or more compactor signatures; and

storing the list of candidate fault locations on one or more computer-readable media.

5. The method of claim 1, further comprising:

generating one or more error vectors based at least in part on the test responses and the expected test response data;

compacting the error vectors in a multiple-input shift register to produce one or more compactor signatures; and

storing the one or more compactor signatures in one or more computer-readable media.

6. The method of claim 5 wherein the multiple-input shift register produces a compactor signature from multiple error vectors input over a plurality of shift cycles.

7. The method of claim 5, wherein the multiple-input shift register produces one compactor signature per test pattern.

8. The method of claim 1, further comprising:

generating an error vector based at least in part on the test responses and the expected test response data, the error vector being generated for a single shift cycle; and

storing the error vector on one or more computer-readable media.

9. The method of claim 1, further comprising loading the test responses into a priority encoder circuit, the test responses comprising test response values from three or more compactor outputs, the priority encoder circuit being configured to detect three or more errors in the test responses input in a single shift cycle.

10. One or more computer-readable media comprising instructions configured to cause a computer to simulate the method of claim 1.

11. An apparatus, comprising:

a plurality of scan chain groups, each scan chain group comprising one or more scan chains and one or more corresponding scan chain group outputs;

a plurality of comparator circuits, each comparator circuit comprising a comparator input and a comparator output;

a multiple-input shift register (MISR) comprising MISR inputs and a MISR output; and

a plurality of compactors, each compactor comprising one or more compactor inputs coupled to the one or more scan chain group outputs of a respective one of the plurality of scan chain groups and further comprising a compactor output coupled directly to a respective one of the MISR inputs and also coupled to the comparator input of a respective comparator.

12. The apparatus of claim 11, further comprising a memory, the memory comprising a first input coupled to the MISR output and a second input coupled to a pattern counter.

13. The apparatus of claim 11, further comprising a plurality of masking gates, each masking gate being coupled between the compactor output of a respective one of the comparators and a respective input of the MISR.

14. An apparatus for testing a plurality of electronic circuits, the apparatus comprising:

a plurality of scan chain groups, each scan chain group comprising one or more scan chains and one or more corresponding scan chain group outputs;

a plurality of comparator circuits, each comparator circuit comprising a comparator input and a comparator output;

an encoder circuit comprising a plurality of encoder inputs and an encoder output, wherein the encoder inputs are coupled to respective comparator outputs; and

a plurality of compactors, each compactor comprising one or more compactor inputs coupled to the scan chain group outputs of a respective one of the scan chain groups and further comprising a compactor output coupled to the comparator input of a respective comparator, the encoder circuit being configured to detect more than two error values output from the compactor outputs.

15. The apparatus of claim 14, wherein the encoder circuit is configured to detect the more than two error values output from the compactor outputs during a single shift cycle.

16. The apparatus of claim 14, wherein the encoder circuit is further configured to detect two or fewer error values output from the compactor outputs.

17. The apparatus of claim 14, further comprising a plurality of masking circuits, each masking circuit having a masking circuit input coupled to the comparator output of a respective compactor and a masking output coupled to respective encoder inputs.

18. The apparatus of claim 14, further comprising a memory coupled to the encoder output.

19. A system for testing a plurality of circuits in a testing system, comprising:

means for receiving masking data for controlling a masking circuit at one of the plurality of circuits; and

means for receiving expected test response data at the one of the plurality of circuits, the masking data and the expected test response data being received simultaneously.

20. The system of claim 19, further comprising:

means for compressing the test responses to produce one or more compactor signatures; and

means for storing the one or more compactor signatures.