High-speed latching technique and application to frequency dividers

• US 20070236267A1
• Filed: 04/05/2006
• Published: 10/11/2007
• Est. Priority Date: 04/05/2006
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Wionics Research
• Inventors: Razavi, Behzad, Soe, Zaw
• Granted Patent: US 7,336,114 B2
• Time in Patent Office: Days
• US Class Current: 327/199
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation

Abstract

The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Claims

1. A current switching circuit comprising;

a load coupled to a first and a second node;

a current regulator coupled to said second and a third node;

an output of an inverter coupled to said second node; and

a clock signal coupled to an input of said inverter.

2. The circuit of claim 1 further comprising;

a first source of potential coupled to said first node; and

a second source of potential coupled to said third node.

3. The circuit of claim 1, wherein

a first logic level of said clock signal forces said load into a first operating state;

and

a second logic level of said clock signal forces said load into a second operating state.

4. The circuit of claim 1 further comprising;

a reset signal to initialize a value held in said load to a known state.

5. The circuit of claim 1, wherein

said load is comprised of a circuit selected from the group consisting of a differential amplifier and a cross-coupled latch.

6. The circuit of claim 5, wherein

an internal load of said load is comprised of a circuit selected from the group consisting of a resistor and an LC resonant circuit.

7. The circuit of claim 1, wherein

said clock signal adjusts an operating characteristic of said load.

8. The circuit of claim 7, wherein

said operating characteristic is comprised of a parameter selected from the group consisting of a power dissipation reduction, performance enhancement and noise reduction.

9. The circuit of claim 1, wherein

said inverter comprises;

a first switchable current regulators coupled between said first and second nodes; and

a second switchable current regulator coupled between said second and third nodes;

wherein said clock signal enables either said first or said second switchable current regulators.

10. The circuit of claim 9, wherein

said current switching circuit is comprised of devices selected from the group consisting of MOS transistors, CMOS transistors and BJT transistors.

11. The circuit of claim 10, wherein

said device of said current regulator is a scaled version of said device of said second switchable current regulator.

12. The circuit of claim 10, wherein

said device of said first switchable current regulator is a scaled version of said device of said second switchable current regulator.

13. A current switching latching apparatus comprising;

at least two current switching circuits;

wherein

a current switching circuit comprises;

a load coupled to a first and a second node;

a current regulator coupled to said second and a third node;

an output of an inverter coupled to said second node;

a clock signal coupled to an input of said inverter; and

a load of said first current switching circuit comprises;

a differential amplifier;

at least one input signal;

at least one output signal; and

a load of said second current switching circuit comprises;

a cross-coupled latch; and

at least one output signal;

whereby

said output signal of said differential amplifier is coupled to said output signal of said cross-coupled latch.

14. The apparatus of claim 13, wherein

said clock signal of said second current switching circuit is essentially 180°

out of phase with said clock signal of said first current switching circuit;

a first logic level of said clock signal of said first current switching circuit forces said differential amplifier into a sensing state; and

a second logic level of said clock signal of said first current switching circuit forces said cross-coupled latch into a holding state.

15. The apparatus of claim 14, wherein

said sensing state amplifies a value of said input signal coupled to said differential amplifier;

and

said holding state latches said value of said output signal in said cross-coupled latch.

16. The apparatus of claim 13, wherein

said plurality of current switching circuits are comprised of devices selected from the group consisting of MOS transistors, CMOS transistors and BJT transistors.

17. The apparatus of claim 13 further comprising;

a first source of potential coupled to said first node of said current switching circuits; and

a second source of potential coupled to said third node of said current switching circuits.

18. The apparatus of claim 13 further comprising;

a reset signal to initialize a value held in said load of said first and said second current switching circuit to a known state.

19. A frequency divider apparatus comprising;

an input terminal and an output terminal;

a current switching circuit comprising;

a load coupled to a first and a second node;

a current regulator coupled to said second and a third node;

an output of an inverter coupled to said second node;

a clock signal coupled to an input of said inverter;

said load having an input port and an output port; and

a current switching latching apparatus comprising;

at least two current switching circuits;

wherein

said load of said first current switching circuit comprises a differential amplifier;

said load of said second current switching circuit comprises a cross-coupled latch;

said output port of said differential amplifier is coupled to said input port of said cross-coupled latch;

said input port of said differential amplifier is coupled to said input terminal;

said output port of said cross-coupled latch is coupled to said output terminal; and

a plurality of current switching latching apparatuses coupled in series forming a closed loop;

wherein

said output terminal of said last current switching latching apparatus is coupled to said input terminal of said first current switching latching apparatus.

20. The apparatus of claim 19, wherein

said clock signal of said first current switching latching apparatus is out of phase with said clock signal of said second current switching latching apparatus;

wherein

a first logic level of said first clock signal forces said first current switching latching apparatus into a capturing state; and

a second logic level of said first clock signal forces said second current switching latching apparatus into a holding state.

21. The apparatus of claim 20, wherein

said out of phase is essentially 180°

out of phase.

22. The apparatus of claim 19, wherein

a frequency generated within said closed loop is lower than an applied frequency of said clock signal.

23. The apparatus of claim 19, wherein

said closed loop contains an odd number of inversions.

24. The apparatus of claim 19 further comprising;

a plurality of output signals;

wherein

said output signals are coupled to a plurality of nodes forming said closed loop.

25. The apparatus of claim 19 further comprising;

a first source of potential coupled to said first node of said current switching circuits; and

a second source of potential coupled to said third node of said current switching circuits.

26. The apparatus of claim 19 further comprising;

a channel select control;

wherein

a first state of said channel select control bypasses a portion of said current switching latching apparatuses coupled in series forming a second closed loop; and

a second state of said channel select control encompasses all of said current switching latching apparatuses coupled in series forming said closed loop.

27. The apparatus of claim 26 further comprising;

a plurality of output signals;

said first state of said channel select control generates a frequency output at said output signals; and

said second state of said channel select control decreases said frequency output at said output signals.

28. A method of adjusting a total current in a load dynamically, the method comprising the steps of;

regulating a first current through a load using a current regulator;

coupling the output of an inverter at a junction between said load and said current regulator;

applying a clock signal to an input of said inverter to introduce an additional current through said load; and

summing said first current and said additional current to form said total current;

thereby adjusting said total current in said load dynamically.

29. The method of claim 28, further comprising the steps of

providing a plurality of potential sources to maintain a flow of said total current.

30. The method of claim 28 wherein;

adjusting said total current adjusts an operating characteristic of said load.

31. A current switching circuit comprising;

a means for regulating a current in a load using a current regulator;

a means for introducing an additional current through said load;

thereby adjusting an overall current in said load dynamically.

32. The circuit of claim 31 further comprising;

a means for providing at least one source of potential to said circuit.

33. The circuit of claim 32, wherein

a clock signal adjusts said additional current means.

34. The circuit of claim 32, wherein

said overall current means adjusts an operating characteristic of the circuit