Method for conditioning a process chamber

• US 20070238199A1
• Filed: 03/31/2006
• Published: 10/11/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Yamashita, Asao
• Granted Patent: US 7,906,032 B2
• Time in Patent Office: Days
• US Class Current: 438/5
• CPC Class Codes: B08B 7/00 Cleaning by methods not provided for in a single other subclass or a single group in this subclass
• CPC Class Codes: B08B 9/00 Cleaning hollow articles by methods or apparatus specially adapted thereto B08B6/00 takes precedence
• CPC Class Codes: C23C 16/4404 Coatings or surface treatment on the inside of the reaction chamber or on parts thereof
• CPC Class Codes: C23C 16/4405 Cleaning of reactor or parts inside the reactor by using reactive gases
• CPC Class Codes: C23C 16/4407 Cleaning of reactor or reactor parts by using wet or mechanical methods
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers

Abstract

A method of conditioning a processing chamber for a production process includes performing a conditioning step at a conditioning process recipe substantially different than a process recipe of the production process, and performing a warm-up process at a warm-up process recipe substantially the same as the process recipe of the production process. The method can be performed after a wet-cleaning process has been performed. The conditioning procedure can allow the maintenance time to be decreased and can cause the etched features to be more accurate.

Claims

1. A method of operating a semiconductor processing system comprising:

determining a first chamber state for a processing chamber, wherein the first chamber state occurs after a first amount of chamber processing time;

taking a processing chamber off-line when the first chamber state indicates a first chamber maintenance procedure is required, wherein the first chamber maintenance procedure comprises a wet cleaning operation in which the processing chamber is not opened and is taken out of production for a first amount of time;

determining a second chamber state for the processing chamber;

performing a first chamber plasma conditioning procedure, wherein the first chamber conditioning procedure comprises a coating operation in which the chamber is not opened and is taken out of production for a second amount of time; and

putting the processing chamber back on-line.

2. The method as claimed in claim 1, further comprising:

determining a cleaning process recipe to change the chamber state of the processing chamber from the first chamber state to a cleaned chamber state;

performing the cleaning process recipe in the processing chamber;

determining a conditioning process to change the state of the processing chamber from the cleaned chamber state to the second chamber state; and

performing the conditioning process on the processing chamber.

3. The method as claimed in claim 2, further comprising:

determining when the chamber state is not the second chamber state; and

performing an additional conditioning process on the processing chamber.

4. The method as claimed in claim 1, wherein at least one of the first and second chamber states is determined based on an optical property of the processing chamber, an electrical property of the processing chamber, or a physical property of the processing chamber, or a combination of two or more thereof.

5. The method as claimed in claim 4, wherein the first chamber state is determined using a voltage measured on a substrate holder.

6. The method as claimed in claim 4, wherein the first chamber state is determined using RF hours data.

7. The method as claimed in claim 1, wherein at least one of the first and second chamber states is determined based on analyzing historical data for the processing chamber.

8. The method as claimed in claim 1, wherein at least one of the first and second chamber states is determined based on predicting a chamber state using a processing chamber model based on process conditions and/or times.

9. The method as claimed in claim 8, further comprising:

determining differences between the predicted chamber state and the second chamber state; and

using the differences to update the chamber conditioning procedure.

10. The method as claimed in claim 1, wherein the processing chamber comprises an etching chamber, a deposition chamber, a cleaning chamber, a developing chamber, a chemical treatment chamber, or a thermal processing chamber, or a combination thereof.

11. The method as claimed in claim 2, wherein the conditioning process comprises a High Dope (HD) conditioning process, a Wafer-Less Dry Clean (WLDC) process, a dry cleaning process, or a warm-up process, or a combination of two or more thereof.

12. A method of conditioning a processing chamber for a production process, the method comprising:

performing a conditioning step at a conditioning process recipe substantially different than a process recipe of the production process; and

performing a warm-up process at a warm-up process recipe substantially the same as the process recipe of the production process.

13. The method as claimed in claim 12, wherein the conditioning step is a High Dope (HD) conditioning process comprising:

positioning a bare silicon wafer on a substrate holder in the processing chamber;

establishing a processing chamber pressure between approximately 10 mTorr and approximately 30 mTorr;

providing a first RF power to an upper electrode in the processing chamber, wherein the first RF power is between approximately 500 Watts and approximately 1200 Watts;

providing a second RF power to the substrate holder in the processing chamber, wherein the second RF power is between approximately 10 Watts and approximately 500 Watts;

flowing a first processing gas into the processing chamber at a first flow rate, wherein the first processing gas comprises CF₄ and the first flow rate ranges between approximately 10 sccm and approximately 100 sccm;

flowing a second processing gas into the processing chamber at a second flow rate, wherein the second processing gas comprises C₄F₈ and the second flow rate ranges between approximately 2 sccm and approximately 25 sccm;

flowing a third processing gas into the processing chamber at a third flow rate, wherein the third processing gas comprises N₂ and the third flow rate ranges between approximately 10 sccm and approximately 100 sccm;

establishing a first temperature for the wafer, wherein the first temperature ranges between approximately 50 degrees C. and approximately 70 degrees C.; and

etching the bare silicon wafer for a first period of time, wherein the first period of time ranges from approximately 2 minutes to approximately 40 minutes.

14. The method as claimed in claim 12, wherein the conditioning step is a waferless dry cleaning (WLDC) process comprising:

positioning a bare silicon wafer on a substrate holder in the processing chamber;

establishing a processing chamber pressure between approximately 50 mTorr and approximately 200 mTorr;

providing a first RF power to an upper electrode in the processing chamber, wherein the first RF power is between approximately 500 Watts and approximately 2500 Watts;

providing a second RF power to the substrate holder in the processing chamber, wherein the second RF power varies from approximately 0 Watts to approximately 100 Watts;

flowing a first processing gas into the processing chamber at a first flow rate, wherein the first processing gas comprises O₂ and the first flow rate ranges between approximately 50 sccm and approximately 200 sccm;

flowing a second processing gas into the processing chamber at a second flow rate, wherein the second processing gas comprises SF₆ and the second flow rate ranges between approximately 100 sccm and approximately 400 sccm;

establishing a first temperature for the wafer, wherein the first temperature ranges between approximately 50 degrees C. and approximately 70 degrees C.; and

etching the bare silicon wafer for a first period of time, wherein the first period of time ranges from approximately 5 seconds to approximately 60 seconds.

15. The method as claimed in claim 12, wherein the conditioning step is a dry cleaning process comprising:

positioning a bare silicon wafer on a substrate holder in the processing chamber;

establishing a processing chamber pressure between approximately 10 mTorr and approximately 30 mTorr;

providing a first RF power to an upper electrode in the processing chamber, wherein the first RF power is between approximately 300 Watts and approximately 1200 Watts;

providing a second RF power to the substrate holder in the processing chamber, wherein the second RF power varies from approximately 0 Watts to approximately 100 Watts;

flowing a first processing gas into the processing chamber at a first flow rate, wherein the first processing gas comprises O₂ and the first flow rate ranges between approximately 100 sccm and approximately 400 sccm;

establishing a first temperature for the wafer, wherein the first temperature ranges between approximately 50 degrees C. and approximately 70 degrees C.; and

etching the bare silicon wafer for a first period of time, wherein the first period of time ranges from approximately 2 minutes to approximately 10 minutes.

16. The method as claimed in claim 12, wherein the warm-up process comprises:

positioning a bare silicon wafer on a substrate holder in the processing chamber;

establishing a processing chamber pressure between approximately 5 mTorr and approximately 20 mTorr;

providing a first RF power to an upper electrode in the processing chamber, wherein the first RF power is between approximately 100 Watts and approximately 500 Watts;

providing a second RF power to the substrate holder in the processing chamber, wherein the second RF power is between approximately 25 Watts and approximately 150 Watts;

flowing a first processing gas into the processing chamber at a first flow rate, wherein the first processing gas comprises CF₄ and the first flow rate ranges between approximately 35 sccm and approximately 140 sccm;

flowing a second processing gas into the processing chamber at a second flow rate, wherein the second processing gas comprises O₂ and the second flow rate ranges between approximately 3 sccm and approximately 15 sccm;

flowing a third processing gas into the processing chamber at a third flow rate, wherein the third processing gas comprises CH₂F₂ and the third flow rate ranges between approximately 3 sccm and approximately 12 sccm;

establishing a first temperature for the wafer, wherein the first temperature ranges between approximately 50 degrees C. and approximately 70 degrees C.; and

etching the bare silicon wafer for a first period of time, wherein the first period of time ranges from approximately 10 seconds to approximately 60 seconds.

17. The method as claimed in claim 12, wherein the warm-up process comprises:

positioning a bare silicon wafer on a substrate holder in the processing chamber;

establishing a processing chamber pressure between approximately 10 mTorr and approximately 40 mTorr;

providing a first RF power to an upper electrode in the processing chamber, wherein the first RF power is between approximately 400 Watts and approximately 1200 Watts;

providing a second RF power to the substrate holder in the processing chamber, wherein the second RF power is between approximately 100 Watts and approximately 400 Watts;

flowing a first processing gas into the processing chamber at a first flow rate, wherein the first processing gas comprises CF₄ and the first flow rate ranges between approximately 25 sccm and approximately 100 sccm;

flowing a second processing gas into the processing chamber at a second flow rate, wherein the second processing gas comprises C₄F₈ and the second flow rate ranges between approximately 6 sccm and approximately 25 sccm;

flowing a third processing gas into the processing chamber at a third flow rate, wherein the third processing gas comprises N₂ and the third flow rate ranges between approximately 25 sccm and approximately 100 sccm;

establishing a first temperature for the wafer, wherein the first temperature ranges between approximately 50 degrees C. and approximately 70 degrees C.; and

etching the bare silicon wafer for a first period of time, wherein the first period of time ranges from approximately 10 seconds to approximately 60 seconds.

18. The method as claimed in claim 12, wherein the warm-up process comprises:

positioning a bare silicon wafer on a substrate holder in the processing chamber;

establishing a processing chamber pressure between approximately 10 mTorr and approximately 40 mTorr;

providing a first RF power to an upper electrode in the processing chamber, wherein the first RF power is between approximately 100 Watts and approximately 400 Watts;

providing a second RF power to the substrate holder in the processing chamber, wherein the second RF power is between approximately 50 Watts and approximately 200 Watts;

flowing a first processing gas into the processing chamber at a first flow rate, wherein the first processing gas comprises HBr and the first flow rate ranges between approximately 250 sccm and approximately 1000 sccm;

flowing a second processing gas into the processing chamber at a second flow rate, wherein the second processing gas comprises O₂ and the second flow rate ranges from approximately 0 sccm to approximately 5 sccm;

establishing a first temperature for the wafer, wherein the first temperature ranges between approximately 50 degrees C. and approximately 70 degrees C.; and

etching the bare silicon wafer for a first period of time, wherein the first period of time ranges from approximately 10 seconds to approximately 60 seconds.

19. The method as claimed in claim 12, wherein the conditioning process comprises:

alternatingly performing a High Dope (HD) conditioning process and a WLDC process using a minimum of ten wafers;

performing a dry cleaning process using at least one wafer; and

performing the warm-up process using at least two wafers.

20. The method as claimed in claim 12, wherein the conditioning step comprises:

performing a High Dope (HD) conditioning step using approximately 800 Watts of top electrode power and approximately 200 Watts of bottom electrode power;

performing a waterless dry cleaning (WLDC) step using approximately 1500 Watts top electrode power and approximately 0 Watts of bottom electrode power;

performing a dry clean step using approximately 650 Watts top electrode power and approximately 0 Watts of bottom electrode power.

21. The method of claim 20, wherein the method of conditioning is completed within approximately 5 hours.

22. The method of claim 20 wherein said method of conditioning is performed after a wet cleaning of the processing chamber.