Simplified pitch doubling process flow

• US 20070238308A1
• Filed: 04/07/2006
• Published: 10/11/2007
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Alapati, Ramakanth, Zhou, Baosuo, Niroomand, Ardavan
• Granted Patent: US 7,902,074 B2
• Time in Patent Office: Days
• US Class Current: 438/743
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

patterning a layer of photoresist material to form a plurality of mandrels in a device array region;

depositing an oxide material over the plurality of mandrels and over a device peripheral region;

forming a pattern of photoresist material over the oxide material in the device peripheral region;

anisotropically etching the oxide material from exposed horizontal surfaces in the device array region; and

selectively etching photoresist material from the device array region and from the device peripheral region.

2. The method of claim 1, wherein the plurality of mandrels include a plurality of mandrel tips, and wherein the pattern of photoresist material overlaps the plurality of mandrel tips.

3. The method of claim 1, further comprising isotropically etching the plurality of mandrels to form a plurality of modified mandrels before depositing the oxide material.

4. The method of claim 3, wherein isotropically etching the plurality of mandrels comprises using an oxygen-containing plasma selected from the group consisting of a SO₂/O₂/N₂/Ar plasma, a Cl₂/O₂/He plasma, and a HBr/O₂/N₂ plasma.

5. The method of claim 1, further comprising anisotropically etching the oxide material from exposed horizontal surfaces in the device peripheral region.

6. The method of claim 1, wherein patterning the layer of photoresist comprises using light having a wavelength selected from the group consisting of 157 nm, 193 nm, 248 nm, and 365 nm.

7. The method of claim 1, wherein patterning the layer of photoresist comprises using nano-imprint lithography.

8. The method of claim 1, wherein the layer of photoresist material patterned in the device array region and the pattern of photoresist material formed in the device peripheral region comprise the same material.

9. The method of claim 1, wherein anisotropically etching the oxide material comprises using a HBr/Cl₂-containing plasma.

10. The method of claim 1, wherein the modified mandrels have a width between about 35 nm and about 70 nm.

11. The method of claim 1, wherein the modified mandrels have a width between about 40 nm and about 50 nm.

12. The method of claim 1, wherein the oxide material is deposited using an atomic layer deposition technique.

13. The method of claim 1, wherein the oxide material is deposited at a temperature less than about 200°

C.

14. The method of claim 1, wherein the oxide material is deposited at a temperature less than about 150°

C.

15. The method of claim 1, wherein the oxide material is deposited at a temperature less than about 125°

C.

16. The method of claim 1, wherein the pattern of photoresist material in the device peripheral region forms a feature selected from the group consisting of a landing pad, a transistor, and an interconnect.

17. The method of claim 1, wherein the layer of photoresist material is patterned over a hard mask layer.

18. The method of claim 1, wherein the layer of photoresist material is patterned over a silicon oxynitride layer that is positioned over a carbon layer.

19. The method of claim 1, wherein the plurality of mandrels have a height between about 50 nm and about 300 nm.

20. The method of claim 1, wherein the mandrels have a width between about 80 nm and about 120 nm.

21. The method of claim 1, wherein the layer of photoresist material comprises a material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.

22. A method of forming a memory device, the method comprising:

forming a plurality of mandrels over a substrate in an array region of the memory device, the mandrels separated by exposed portions the substrate;

depositing a spacer material over the mandrels, over the exposed portions of the substrate, and over a peripheral region of the memory device;

depositing a peripheral mask over the spacer material in the peripheral region of the memory device; and

anisotropically etching the spacer material from exposed horizontal surfaces, thereby leaving spacer material remaining (a) on vertical sidewalls of the mandrels in the array region, and (b) between the substrate and the peripheral mask in the peripheral region.

23. The method of claim 22, wherein the substrate includes a hard mask directly under the spacer material.

24. The method of claim 22, wherein the partiality of mandrels include a plurality of mandrel end portions, wherein the peripheral mask is deposited over the plurality of mandrel end portions.

25. The method of claim 22, wherein the peripheral mask is patterned in the peripheral region of the memory device to form a feature selected from the group consisting of a landing pad, a transistor, and an interconnect.

26. The method of claim 22, wherein the spacer material is deposited at a temperature less than about 75°

C.

27. The method of claim 22, further comprising removing the mandrels, thereby leaving a pattern of spacers positioned over the substrate in the array region and a pattern of spacer material positioned over the substrate in the peripheral region.

28. The method of claim 27, further comprising transferring the pattern of spacers into the substrate.

29. The method of claim 22, wherein the mandrels and the peripheral mask comprise a photoresist material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.

30. The method of claim 29, wherein the mandrels and the peripheral mask comprise the same material.

31. The method of claim 22, wherein the spacer material is an oxide material.

32. The method of claim 22, wherein the mandrels are formed using a photolithographic technique and a pitch doubling technique.

33. The method of claim 32, wherein the mandrels form a pattern having a pitch that is between about ½

F and about F, wherein F is the minimum resolvable feature size of the photolithographic technique.

34. The method of claim 32, wherein the mandrels form a pattern having a pitch that is between about 35 nm and about 70 nm.

35. A method of forming an integrated circuit, the method comprising:

forming a plurality of mandrels on a hard mask layer in an array region, wherein the mandrels comprise a photoresist material;

depositing an oxide material over the array region and over a peripheral region that surrounds the array region, wherein the oxide material covers the plurality of mandrels;

forming a pattern of photoresist material over the oxide material in the peripheral region;

anisotropically etching the oxide material from horizontal surfaces in the array region; and

removing exposed photoresist material from the array region and the peripheral region after anisotropically etching the oxide material.

36. The method of claim 35, wherein the hard mask layer comprises a material selected from the group consisting of silicon, silicon nitride and silicon oxynitride.

37. The method of claim 35, wherein the plurality of mandrels are formed over the hard mask layer that is positioned over a carbon layer.

38. The method of claim 35, wherein the plurality of mandrels are formed over the hard mask layer that is positioned over a semiconductor substrate.

39. The method of claim 35, wherein the plurality of mandrels comprise a material selected from the group consisting of argon fluoride photoresist and krypton fluoride photoresist.

40. The method of claim 35, wherein the oxide material is deposited at a temperature less than about 100°

C.

41. The method of claim 35, further comprising isotropically etching the plurality of mandrels before depositing the oxide material.

42. The method of claim 41, wherein the plurality of mandrels are isotropically etched using an oxygen-containing plasma selected from the group consisting of a SO₂/O₂/N₂/Ar plasma, a Cl₂/O₂/He plasma, and a HBr/O₂/N₂ plasma.

43. The method of claim 41, wherein the plurality of mandrels are isotropically etched to have a width between about 35 nm and about 70 nm.

44. The method of claim 41, wherein the plurality of mandrels are isotropically etched to have a width between about 40 nm and about 50 nm.

45. The method of claim 35, wherein removing exposed photoresist material from the peripheral region exposes a patterned oxide material.

46. The method of claim 45, wherein the patterned oxide material defines a feature selected from the group consisting of a landing pad, a transistor, and an interconnect.

47. The method of claim 35, wherein anisotropically etching the oxide material from exposed horizontal surfaces comprises using a HBr/Cl₂-containing plasma.

48. The method of claim 35, wherein the plurality of mandrels are formed by patterning the photoresist material using light having a wavelength selected from the group consisting of 157 nm, 193 nm, 248 nm and 365 nm.

49. The method of claim 35, wherein the photoresist material that comprises the mandrels in the device array region and the photoresist material patterned over the oxide material in the device peripheral region comprise the same material.

50. A method of integrated circuit fabrication, the method comprising:

using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer in an integrated circuit array region, wherein the mandrels comprise a photoresist material; and

forming a pattern of spacers around the plurality of elongate mandrels, wherein the pattern of spacers have a pitch that is smaller than a minimum resolvable pitch of the lithographic technique, and wherein the spacers are formed from an oxide material that is deposited at a temperature less than about 100°

C.

51. The method of claim 50, wherein the oxide material is deposited at a temperature less than about 80°

C.

52. The method of claim 50, wherein the oxide material is deposited at a temperature less than about 30°

C.

53. The method of claim 50, further comprising transferring the pattern of spacers into the hard mask layer.

54. The method of claim 53, wherein transferring the pattern of spacers into the hard mask layer further comprises exposing a portion of a substrate that underlies the hard mask layer.

55. The method of claim 50, wherein the pattern of spacers comprises a pattern of spacer loops formed around the elongate mandrels.

56. The method of claim 50, wherein the hard mask layer comprises a material selected from the group consisting of silicon, silicon nitride and silicon oxynitride.

57. The method of claim 50, wherein the hard mask layer comprises a dielectric antireflective coating.

58. The method of claim 50, wherein the hard mask layer is formed over a semiconductor substrate.

59. The method of claim 50, wherein the hard mask layer is formed over a semiconductor substrate and an amorphous carbon layer.

60. The method of claim 50, wherein the plurality of elongate mandrels have a height between about 50 nm and about 300 nm.

61. The method of claim 50, wherein the plurality of elongate mandrels have a height between about 200 nm and about 250 nm.

62. The method of claim 50, wherein the plurality of elongate mandrels comprise a material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.

63. The method of claim 50, wherein the pattern of spacers has a pitch between about 70 nm and about 120 nm.

64. The method of claim 50, wherein the patterns has a pitch between about 80 nm and about 100 nm.

65. The method of claim 50, wherein the oxide material is deposited using an atomic layer deposition technique.

66-81. -81. (canceled)