CONFIGURABLE IC WITH ROUTING CIRCUITS WITH OFFSET CONNECTIONS

• US 20070241783A1
• Filed: 03/15/2005
• Published: 10/18/2007
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Hutchings, Brad, Schmit, Herman, Huang, Randy
• Granted Patent: US 7,295,037 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Claims

1-16. -16. (canceled)

17. An electronic device comprising:

a configurable integrated circuit (“

IC”

) comprising;

a) a plurality of configurable tiles arranged in a tile arrangement,

b) each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

c) wherein at least a first routing circuit of a first tile has a direct connection with a second routing circuit of a second tile that is not aligned horizontally or vertically with the first tile in the tile arrangement, and through the direct connection, the first routing circuit provides an input signal to the second routing circuit; and

d) wherein the second routing circuit comprises a first input and a second input, wherein the first input is coupled to the direct connection, and wherein the second input is for receiving signals from within said second tile.

18. The electronic device of claim 17, wherein a plurality of routing circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

19. The electronic device of claim 17, wherein the IC further comprises:

a third tile, wherein a third routing circuit of said third tile has a second direct connection to said second routing circuit; and

wherein the second routing circuit further comprises a third input for receiving signals through said second direct connection.

20. The electronic device of claim 17, wherein the IC further comprises:

a third tile, wherein a third routing circuit of said third tile has a second direct connection to said second routing circuit; and

wherein the second routing circuit further comprises an output for sending signals through said second direct connection.

21. The electronic device of claim 17, wherein the second tile does not neighbor the first tile.

22. The electronic device of claim 17, wherein the direct connection does not include any intervening circuits.

23. The electronic device of claim 17, wherein the direct connection includes a set of wire segments and a set of vias.

24. The electronic device of claim 17, wherein each of a plurality of routing circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.

25. A configurable integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement,

each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

wherein at least a first routing circuit of a first tile has a direct connection with a second routing circuit of a second tile that is not aligned horizontally or vertically with the first tile in the tile arrangement, and through the direct connection, the first routing circuit provides an input signal to the second routing circuit; and

wherein the second routing circuit comprises a first input and a second input, wherein the first input is coupled to the direct connection, and wherein the second input is for receiving signals from within said second tile.

26. The configurable integrated circuit (“

IC”

) of claim 25, further comprising;

a third tile, wherein a third routing circuit of said third tile has a second direct connection to said second routing circuit; and

wherein the second routing circuit further comprises a third input for receiving signals through said second direct connection.

27. The configurable integrated circuit (“

IC”

) of claim 25, further comprising;

a third tile, wherein a third routing circuit of said third tile has a second direct connection to said second routing circuit; and

wherein the second routing circuit further comprises an output for sending signals through said second direct connection.

28. The configurable IC of claim 25, wherein a plurality of routing circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile in the tile arrangement and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

29. The configurable IC of claim 25, wherein each of a plurality of routing circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.

30. The configurable IC of claim 25, wherein the direct connection does not include any intervening circuits.

31. The configurable IC of claim 25, wherein the direct connection includes a set of wire segments and a set of vias.

32. The configurable IC of claim 25, wherein the second tile does not neighbor the first tile.