Power Semiconductor Component, Power Semiconductor Device As Well As Methods For Their Production

• US 20070246838A1
• Filed: 04/18/2007
• Published: 10/25/2007
• Est. Priority Date: 04/20/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hoeglauer, Josef, Otremba, Ralf, Schloegel, Xaver
• Granted Patent: US 7,667,326 B2
• Time in Patent Office: Days
• US Class Current: 257/781
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24246 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/37155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48491 being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns

Abstract

A power semiconductor component (2) has a semiconductor body with a front face (7) and a rear face (9). The front face (7) has a front-face metallization (8), which provides at least one first contact pad (11). A structured metal seed layer (14) is provided as the front-face metallization (8), is arranged directly on the semiconductor body, and has a thickness d, where 1 nm≦d≦0.5 μm.

Claims

1. A power semiconductor component comprising a semiconductor body with a front face and a rear face, the front face having a structured metal seed layer as a front-face metallization which provides at least one first contact pad, wherein the structured metal seed layer is arranged directly on the semiconductor body and has a thickness d where 1 nm≦

d≦

0.5 μ

m.

2. The power semiconductor component according to claim 1, wherein the thickness of the metal seed layer is 1 nm≦

d≦

200 nm, preferably 10 nm≦

d≦

100 nm.

3. The power semiconductor component according to claim 1, wherein the metal seed layer comprises Cr, Ni, Pd or Ti.

4. The power semiconductor component according to claim 1, wherein the metal seed layer is free of aluminum.

5. The power semiconductor component according to claim 1, wherein the power semiconductor component is a vertical power semiconductor component, the front-face metallization furthermore providing at least one control contact pad, and the rear face having at least one second contact pad.

6. The power semiconductor component according to claim 1, wherein the power semiconductor component is a lateral power semiconductor component, with the front-face metallization furthermore providing at least one control contact pad and at least one second contact pad.

7. The power semiconductor component according to claim 1, wherein the control contact pad is provided in the form of a strip.

8. The power semiconductor component according to claim 1, wherein the power semiconductor component is a MOSFET, a BJT or an IGBT.

9. The power semiconductor component according to claim 1,

wherein the power semiconductor component is a diode.

10. The power semiconductor component according to claim 1, wherein a contact layer is arranged on the metal seed layer, and consists of one or more electrochemically applied metals.

11. The power semiconductor component according to claim 1, wherein the contact layer consists essentially of copper, nickel or an alloy thereof.

12. The power semiconductor component according to claim 10, wherein the contact layer is free of aluminum.

13. The power semiconductor component according to claim 10, wherein the contact layer has a thickness a, where 10 μ

m≦

a≦

500 μ

m, preferably 10 μ

m≦

a≦

100 μ

m.

14. A semiconductor wafer having a plurality of component positions, which are arranged in rows and columns and each provide a power semiconductor component according to claim 1.

15. A power semiconductor device having at least one power semiconductor component according to claim 1.

16. A power semiconductor device comprising:

a power semiconductor component according to claim 1,

a leadframe having a plurality of contact connections and a chip carrier, the contact connections each having an inner contact pad and an outer contact pad,

an isolation film with an upper face and a lower face, the rear face of the semiconductor component being mounted on the chip carrier, and the isolation film being arranged on the front face of the semiconductor component and extending from the front face to an upper face of at least one contact connection, and bridging a distance between the chip carrier and the contact connection, and

an electrically conductive connecting layer being arranged on the upper face of the isolation film, and electrically connecting a first contact pad and the front-face metallization to at least one contact connection.

17. The power semiconductor device according to claim 16, wherein the isolation film comprises at least one through-opening, which exposes at least one area of the first contact pad.

18. The power semiconductor device according to claim 16, wherein the isolation film comprises at least one through-opening, which exposes at least one area of the inner contact pad of the contact connection.

19. The power semiconductor device according to claim 16, wherein a layer which is produced by means of sputtering or vapor deposition is provided as the connecting layer.

20. The power semiconductor device according to claim 16, wherein a multiple layer is provided as the connecting layer.

21. The power semiconductor device according to claim 20, wherein a lowermost layer of the connecting layer is an adhesion-promoting layer, and an uppermost layer of the connecting layer is a low-resistance layer.

22. The power semiconductor device according to claim 21, wherein the lowermost layer is a layer which is produced by means of sputtering or vapor deposition, and the uppermost layer is an electrochemically applied layer.

23. The power semiconductor device according to claim 16, wherein the connecting layer consists essentially of copper, nickel or an alloy thereof.

24. The power semiconductor device according to claim 20, wherein the lowermost layer and/or the uppermost layer of the connecting layer consists essentially of copper, nickel or an alloy thereof.

25. The power semiconductor device according to claim 16, wherein the connecting layer is free of aluminum.

26. The power semiconductor device according to claim 16, wherein the connecting layer has a thickness b, where 10 μ

m≦

b≦

500 μ

m, preferably 10 μ

m≦

b≦

100 μ

m.

27. The power semiconductor device according to claim 16, wherein the connecting layer comprises at least two connecting areas, which are electrically isolated from one another and each electrically connect one contact pad on the front-face metallization to at least one contact connection of the leadframe.

28. The power semiconductor device according to claim 16, wherein at least one control contact pad, which is in the form of a strip, is arranged on the front face of the power semiconductor component and is electrically connected essentially over its entire length, via an area of the connecting layer, to at least one contact connection of the leadframe.

29. The power semiconductor device according to claim 16, wherein the power semiconductor device furthermore has a plastic housing compound, which envelops the semiconductor component as well as the isolation film and the connecting layer.

42. A method for production of a power semiconductor device, comprising the steps:

providing a power semiconductor component according to claim 1,

providing a leadframe having a plurality of contact connections and a chip carrier, the contact connections each having an inner contact pad and an outer contact pad,

providing an isolation film, having an upper face and a lower face,

fixing the power semiconductor component by its rear face on an upper face of the chip carrier of the leadframe,

applying an isolation film to the upper face of the semiconductor component, exposing at least the first contact pads and partially exposing the upper faces of the contact connections, the isolation film extending from the front face of the power semiconductor component to an upper face of at least one contact connection, and bridging a distance between the chip carrier and the contact connection, and

applying an electrically conductive connecting layer to an upper face of the isolation film, with the connecting layer extending between the first contact pad and the surface of the contact connection.

43. The method according to claim 42, wherein in order to fix the power semiconductor component, the power semiconductor component is soldered on the chip carrier.

44. The method according to claim 43, wherein in order to fix the power semiconductor component, the power semiconductor component is adhesively bonded to the chip carrier.

45. The method according to claim 42, wherein in order to expose the first contact pad and in order to partially expose the upper faces of the contact connections, the isolation film is stamped before application.

46. The method according to claim 42, wherein in order to expose the first contact surfaces and in order to partially expose the upper faces of the contact connections, the isolation film is structured after application.

47. The method according to claim 46, wherein the isolation film is structured by means of laser ablation.

48. The method according to claim 42, wherein the connecting layer is applied layer-by-layer.

49. The method according to claim 48, wherein a first layer of the connecting layer is deposited by a sputtering method.

50. The method according to claim 48, wherein a second layer of the connecting layer is deposited by an electrochemical method.

51. The method according to claim 48, wherein an adhesion-promoting and/or a diffusion-constraining electrically conductive layer is applied within the first layer.

52. The method according to claim 42, wherein the previously assembled components are embedded in a plastic housing compound, the outer contacts projecting out of the plastic housing compound.

30. A method for production of front-face metallization for a power semiconductor component, comprising the steps:

providing a power semiconductor component which has a semiconductor body with a front face and a rear face, and

applying a metal seed layer to the front face of the body of the semiconductor component in order to form at least one contact pad, the metal seed layer being deposited with a thickness d, where 1 nm≦

d≦

0.5 μ

m.

31. The method according to claim 30, wherein the metal seed layer is deposited with a thickness of 1 nm≦

d≦

200 nm, preferably 10 nm≦

d≦

100 nm.

32. The method according to claim 30, wherein the metal seed layer is deposited by means of sputtering or vapor deposition.

33. The method according to claim 30, wherein a closed metal seed layer is deposited, and is then structured, in order to form at least one first contact pad.

34. The method according to claim 30, wherein a photosensitive lacquer layer, containing metal, is applied to the front face, and is then irradiated in order to produce metal seeds, for the application of the metal seed layer.

35. The method according to claim 34, wherein the photosensitive lacquer layer containing metal is irradiated by means of a UV laser, and excimer laser or a UV emitter.

36. The method according to claim 34, wherein the photosensitive lacquer layer containing metal is selectively irradiated in order to form separate contact pads which are electrically isolated from one another.

37. The method according to claim 34, wherein the photosensitive lacquer layer containing metal is applied to the front face by printing, spraying or spin-coating.

38. The method according to claim 30, wherein a contact layer is electrochemically applied to the metal seed layer in order to form at least one contact.

39. The method according to claim 38, wherein the contact layer is applied by electroless deposition.

40. The method according to claim 38, wherein the contact layer is deposited with a thickness a, where 10 μ

m≦

a≦

500 μ

m, preferably 10 μ

m≦

a≦

100 μ

m.

41. The method according to claim 38, wherein after deposition of the contact layer, the power semiconductor component is separated from a wafer.