Semiconductor device with a barrier layer and a metal layer

• US 20070254475A1
• Filed: 07/03/2007
• Published: 11/01/2007
• Est. Priority Date: 02/17/2004
• Status: Active Grant

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okayama, Yoshio, Suzuki, Akira, Kameyama, Koujiro
• Granted Patent: US 7,759,247 B2
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a pad electrode layer comprising a first barrier layer formed on a top surface of the semiconductor substrate and a metal layer formed on the first barrier layer;

attaching a supporting member to the top surface of the semiconductor substrate;

forming a via hole in the semiconductor substrate from a back surface of the semiconductor substrate to expose the first barrier layer; and

forming a wiring layer on the back surface of the semiconductor substrate so that the wiring layer extends into the via hole to connect with the first barrier layer.

2. The method of claim 1, wherein the wiring layer is formed so as to substantially fill up the via hole.

3. The method of claim 1, wherein the wiring layer is formed so as to fill the via hole only partially.

4. The method of claim 1, wherein the wiring layer is formed by plating or by sputtering.

5. The method of claim 1, further comprising forming a conductive terminal on the wiring layer.

6. The method of claim 1, wherein the first barrier layer is made of titanium nitride, titanium tungsten, tantalum nitride, a refractory metal, a metal compound layer having a high melting point or a combination thereof.

7. The method of claim 1, further comprising forming a second barrier layer to cover the wiring layer.

8. The method of claim 7, wherein the second barrier layer is made of titanium nitride, titanium tungsten, tantalum nitride, a refractory metal, a metal compound layer having a high melting point or a combination thereof.

9. The method of claim 1, wherein the metal layer of the pad electrode layer is made of aluminum or an aluminum alloy.

10. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a pad electrode layer comprising a first barrier layer formed on a top surface of the semiconductor substrate and a metal layer formed on the first barrier layer;

forming a via hole in the semiconductor substrate from a back surface of the semiconductor substrate to expose the first barrier layer; and

forming a wiring layer on the back surface of the semiconductor substrate so that the wiring layer extends into the via hole to connect with the first barrier layer.