Inhibition of stimulation notification

• US 20070255347A1
• Filed: 10/30/2006
• Published: 11/01/2007
• Est. Priority Date: 04/28/2006
• Status: Abandoned Application

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Torgerson, Nathan A., Marks, William J.
• Application Number:
  US11/589,698
• Publication Number:
  US 20070255347A1
• Time in Patent Office: Days
• US Class Current: 607/59
• CPC Class Codes: A61N 1/0534 Electrodes for deep brain stimulation
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/37258 Alerting the patient
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware

Abstract

The disclosure is directed to techniques for delivering electrical stimulation for patient notification. An implantable medical device (IMD) may deliver patient notification stimulation via one or more device site electrodes, e.g., electrodes located proximate to an implant site for the IMD, configured as cathodes. Anodes for delivery the patient notification stimulation may be located in an electrode array that is provided by one or more leads and located distally from the implant site, e.g., an electrode array located at one or more target sites for delivery of stimulation therapy. In some embodiments, the IMD may inhibit the patient notification stimulation for a period in response to input from the patient, and then resume the stimulation at the end of the period. In this manner, the notification stimulation may be “snoozed” like an alarm clock. When the stimulation resumes, it may be different, e.g., more urgent, then prior to inhibition.

Claims

1. (canceled)

2. An integrated multimedia system having a multimedia processor disposed in an integrated circuit, said system comprising:

a first host processor system coupled to said multimedia processor;

a second local processor disposed within said multimedia processor for controlling the operation of said multimedia processor;

a data transfer switch disposed within said multimedia processor and coupled to said second processor for transferring data to various modules of said multimedia processor, at least one of which is a data cache, wherein said data transfer switch is configured to transfer data in either direction between said data cache and a module within said multimedia processor as requested by said modules;

a data streamer coupled to said data transfer switch, and configured to schedule simultaneous data transfers among the various modules disposed within said multimedia processor, in accordance with corresponding channel allocations;

an interface unit coupled to said data streamer having a plurality of input/output (I/O) device driver units; and

a plurality of external I/O devices coupled to said plurality of I/O device driver units via a multiplexer.

3. The system in accordance with claim 2, wherein each one of said external I/O devices is controlled by a corresponding one of said I/O device driver units.

4. The system in accordance with claim 3, wherein one of said external I/O devices is an NTSC decoder.

5. The system in accordance with claim 3, wherein one of said external I/O devices is an NTSC encoder.

6. The system in accordance with claim 3, wherein one of said external I/O devices is a demodulator unit configured to demodulate wireless communications signals.

7. The system in accordance with claim 6, wherein said demodulator unit communicates with said multimedia processor in accordance with a transport channel interface arrangement.

8. The system in accordance with claim 3, wherein said multimedia processor provides video signals and three dimensional graphic signals to an external video display device.

9. The system in accordance with claim 3, wherein one of said external I/O devices is an ISDN interface.

10. The system in accordance with claim 3, wherein one of said external I/O devices is an audio coder and decoder (CODEC) unit.

11. The system in accordance with claim 2, wherein said data cache is directly coupled to said second local processor and said data transfer switch.

12. The system in accordance with claim 2, wherein said plurality of modules among which said streamer configures to schedule simultaneous data transfers include the interface unit which is capable of controlling the external I/O devices, and a memory controller which is capable of controlling an external memory.

13. The system in accordance with claim 12, wherein said plurality of modules among which said data streamer configures to schedule simultaneous data transfers further include another interface unit which is capable of communicating with said first processor.

14. The system in accordance with claim 2, wherein said data transfer switch further comprises a plurality of buses.

15. An integrated multimedia system having a multimedia processor disposed in an integrated circuit, said system comprising:

a processor disposed within said multimedia processor for controlling the operation of said multimedia processor;

a data transfer switch disposed within said multimedia processor and coupled to said processor for transferring data to various modules of said multimedia processor, at least one of which is a data cache, wherein said data transfer switch is configured to transfer data in either direction between said data cache and a module within said multimedia processor as requested by said modules;

a data streamer coupled to said data transfer switch, and configured to schedule simultaneous data transfers among the various modules disposed within said multimedia processor, in accordance with corresponding channel allocations;

an interface unit coupled to said data streamer having a plurality of input/output (I/O) device driver units; and

a plurality of external I/O devices coupled to said plurality of I/O device driver units via a multiplexer.

16. The system in accordance with claim 15, wherein each one of said external I/O devices is controlled by a corresponding one of said I/O device driver units.

17. The system in accordance with claim 16, wherein one of said external I/O devices is an NTSC decoder.

18. The system in accordance with claim 16, wherein one of said external I/O devices is an NTSC encoder.

19. The system in accordance with claim 16, wherein one of said external I/O devices is a demodulator unit configured to demodulate wireless communications signals.

20. The system in accordance with claim 19, wherein said demodulator unit communicates with said multimedia processor in accordance with a transport channel interface arrangement.

21. The system in accordance with claim 16, wherein said multimedia processor provides video signals and three dimensional graphic signals to an external video display device.

22. The system in accordance with claim 16, wherein one of said external I/O devices is an ISDN interface.

23. The system in accordance with claim 16, wherein one of said external I/O devices is an audio coder and decoder (CODEC) unit.

24. The system in accordance with claim 15, wherein said data cache is directly coupled to said processor and said data transfer switch.

25. The system in accordance with claim 15, wherein said plurality of modules among which said data streamer configures to schedule simultaneous data transfers include the interface unit which is capable of controlling the external I/O devices, and a memory controller which is capable of controlling an external memory.

26. The system in accordance with claim 25, wherein said plurality of modules among which said data streamer configures to schedule simultaneous data transfers further include another interface unit which is capable of communicating with a first host processor.

27. The system in accordance with claim 15, wherein said data transfer switch further comprises a plurality of buses.