Error detection in physical interfaces for point-to-point communications between integrated circuits

• US 20070260965A1
• Filed: 03/09/2006
• Published: 11/08/2007
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Schmidt, Brian, Butcher, Lawrence
• Granted Patent: US 7,694,204 B2
• Time in Patent Office: Days
• US Class Current: 714/799
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0092 Error control systems characterised by the topology of the transmission link
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.

Claims

1. An apparatus for detecting errors in a physical interface that facilitates data communications between integrated circuits (“

ICs”

), the apparatus comprising;

a decoder configured to decode a subset of encoded data bits to yield decoded data bits; and

a physical interface (“

PI”

) error detection bit extractor configured to extract a physical interface error detection bit from said decoded data bits, said physical interface error detection bit being used to determine whether said encoded data bits include at least one erroneous data bit as an error.

2. The apparatus of claim 1 further comprising:

an error detector configured to operate within a physical layer to detect said error,

wherein said subset of said encoded data bits includes an embedded clock.

3. The apparatus of claim 2 wherein said error detector performs error detection earlier than at a data link layer or at any upper layer of the Open Systems Interconnection (“

OSI”

) seven layer reference model above said physical layer.

4. The apparatus of claim 2 wherein said physical interface error detection bit is a parity bit, said error detector being configured to check a parity of said encoded data bits and to detect an error if said parity is noncompliant.

5. The apparatus of claim 2 wherein said physical interface error detection bit is a portion of an error-detection code.

6. The apparatus of claim 5 wherein said error-detection code is a cyclic redundancy check (“

CRC”

) checksum, said error detector being configured to accumulate said physical interface error detection bit and other physical interface error detection bits from other subsets of said encoded data bits to reconstruct said error-detection code.

7. The apparatus of claim 6 wherein said error detector is configured to:

generate said CRC checksum from said physical interface error detection bit and said other physical interface error detection bits, and is configured further to;

compare said CRC checksum against said error-detection code to determine whether at least one error has occurred.

8. The apparatus of claim 6 wherein said physical interface error detection bit and each of said other physical interface error detection bits are received at said apparatus concurrent with said subset of said encoded data bits and each of said other subsets of said encoded data bits, respectively, thereby decreasing the time said apparatus receives said error-detection code that otherwise is appended to follow said encoded data bits.

9. The apparatus of claim 2 further comprising an error corrector configured to correct said error.

10. The apparatus of claim 9 wherein said error corrector is configured either to request a retransmission of said subset of said encoded data bits or to signal an application-specific module of the detection of said error so that said application-specific module can resolve said error.

11. The apparatus of claim 1 wherein said subset of said encoded data bits includes N+m data bits and said decoded data bits include N application data bits, where m represent the number of extra bits used for at least embedding an asynchronous clock and said physical interface error detection bit in said encoded data bits.

12. The apparatus of claim 11 wherein said apparatus is configured to receive said encoded data bits as N+2 data bits into one or more input terminals and to provide N application data bits and at least one physical interface error detection bit at one or more output terminals.

13. The apparatus of claim 12 wherein N is 8 and said apparatus is configured as an 8B/10B decoder that provides said physical interface error detection bit for error detection.

14. An apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“

ICs”

), the apparatus comprising;

an N bit-to-N+2 (“

N bit/N+2”

) bit physical layer (“

PHY”

) encoder configured to;

insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and

encode said N+1 unencoded data bits to yield N+2 encoded data bits; and

an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit,

wherein N represents any integer number of data bits.

15. The apparatus of claim 14 further comprising a serializer configured to serialize said N+2 encoded data bits to form serial N+2 encoded data bits, thereby interleaving error-detection data bits with other data bits.

16. The apparatus of claim 14 further comprising storage to store a group of data bits that include said N application data bits, said error-detection code generator being configured to examine said group of data bits to generate said error-detection code.

17. The apparatus of claim 16, further comprising a transmitter error corrector configured to retransmit one or more subsets of said group of data bits when said transmitter error corrector receives a request for retransmission.

18. The apparatus of claim 14 wherein N is one of 8, 12, 18, 64 and 128.

19. A physical interface formed as an integrated circuit (“

IC”

) on a first substrate portion to detect transmission errors in data exchanged with another IC formed on a second substrate portion, the physical interface comprising;

a plurality of input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to said another IC; and

one or more error recovery modules coupled between said plurality of input ports and output ports,

wherein a first error recovery module of said one or more error recovery modules is coupled between at least one of said first subset of input ports and at least one of said first subset of output ports.

20. The physical interface of claim 19 wherein said first error recovery module includes a physical layer (“

PHY”

) decoder configured to detect errors in said in-bound encoded data bits and to initiate an action to correct said errors

21. The physical interface of claim 20 wherein said PHY decoder is an N+2 bit/N bit decoder.

22. The physical interface of claim 20 wherein said plurality of input ports and output ports include a second subset of input ports configured to receive out-bound unencoded data bits from said another IC and a second subset of output ports configured to transmit out-bound encoded data bits, wherein a second error recovery module of said one or more error recovery modules is coupled between at least one of said second subset of input ports and at least one of said second subset of output ports, said second error recovery module including a PHY encoder configured to generate error-detection codes for said out-bound encoded data bits.

23. The physical interface of claim 22 wherein said PHY encoder is an N bit/N+2 bit encoder, and said another IC is a core IC.

24. The physical interface of claim 22 further comprising a memory IC as said another IC, wherein said first subset of output ports are coupled to address bus inputs of said memory IC to communicate said in-bound decoded data bits as address bits and said second subset of input ports are coupled to data bus outputs of said memory IC to communicate said out-bound decoded data bits as memory data bits.

25. The physical interface of claim 19 wherein said first substrate further comprises an input-output (“

I/O”

) ring in which said physical interface is formed, wherein said first substrate portion and said second substrate portion are on the same substrate.

26. A method for decoding data bits to at least detect errors at a physical interface, the method comprising:

decoding a subset of an encoded bit stream having an embedded asynchronous clock to yield decoded data bits;

extracting a physical interface error detection bit from said decoded data bits;

determining said encoded bit stream includes an incorrect bit based on at least said physical interface error detection bit; and

correcting said error at said physical interface.

27. The method of claim 26 wherein determining said subset of said encoded bit stream includes said incorrect bit further comprises:

determining a parity of a subset of said encoded bit stream with said physical interface error detection bit; and

indicating said error is present if said parity does not comply with a predetermined parity.

28. The method of claim 26 wherein determining said subset of said bit stream includes said incorrect bit comprises:

combining said physical interface error detection bit with other physical interface error detection bits to form a first error detection code;

generating a second error detection code based on application data bits from said decoded data bits and other application data bits from other decoded data bits decoded from other subsets of said bit stream;

comparing said first error detection code against said second error detection code; and

indicating said error is present if said second error detection code does not match said first error detection code.

29. The method of claim 26 wherein correcting said error comprises requesting a retransmission of at least said subset of said encoded bit stream.

30. The method of claim 26 further comprising:

passing said decoded data bits if no error is detected to a framer for assembly into a frame;

extracting a contiguous set of bits constituting a Frame Check Sequence (“

FCS”

) code for said frame;

computing a Cyclic Redundancy Check (“

CRC”

) checksum; and

comparing said FCS code with said CRC checksum to determine whether another error exists.

31. A high-speed serial communications link between at least two integrated circuits (“

ICs”

) comprising;

a physical medium for conveying communications data;

a transmitter device coupled to a first end of said physical medium, said transmitter device includes an N bit/N+2 bit encoder that generates encoded data bits with physical interface error detection bits encoded therein; and

a receiver device coupled to a second end of said physical medium, said receiver device includes;

an N+2 bit/N bit decoder that decodes said encoded data bits, and

an error detector configured to determine an error using said physical interface error detection bits.

32. The high-speed serial communications link of claim 31 wherein said error detector is configured to detect errors due to signal-to-noise ratios (“

SNRs”

) below that which is required for being substantially immune from external noise.

33. The high-speed serial communications link of claim 31 wherein said transmitter device is a transition-minimized differential signaling (“

TMDS”

) transmitter and said receiver device is a TMDS receiver.

34. The high-speed serial communications link of claim 31 wherein said transmitter device is a high-definition multimedia interface (“

HDMI”

) transmitter and said receiver device is an HDMI receiver.

35. The high-speed serial communications link of claim 31 wherein said transmitter device is an Ethernet transmitter and said receiver device is an Ethernet receiver for multi-Gigabit data rates, wherein said multi-Gigabit data rates includes 10 Gbps Ethernet (“

10 GbE”

).

36. The high-speed serial communications link of claim 31 wherein said transmitter device is a serial advanced technology attachment (“

SATA”

) transmitter and said receiver device is an SATA receiver.

37. A physical interface for detecting transmission errors at a physical layer during point-to-point communications via parallel data link, the physical interface comprising:

a parallel port for receiving parallel communications data via said parallel data link, a subset of said parallel communications data including a physical interface error detection bit;

an external clock input configured to receive an external clock to synchronize the reception of said parallel communications data; and

a physical interface error detector configured to use said physical interface error detection bit to determine whether said parallel communications data includes an incorrect bit as an error; and

an error corrector configured to correct said error at said physical interface.

38. The physical interface of claim 37 further comprising:

a buffer to temporarily store application data bits of said parallel communications data until said physical interface error detector determines that said error does not exist; and

a buffer output for said buffer,

wherein said buffer is disposed at a physical layer and said buffer output is disposed substantially within an upper layer.