METHODS FOR FORMING THROUGH-WAFER INTERCONNECTS AND DEVICES AND SYSTEMS HAVING AT LEAST ONE DAM STRUCTURE

• US 20070262424A1
• Filed: 07/23/2007
• Published: 11/15/2007
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hiatt, W.
• Granted Patent: US 7,833,894 B2
• Time in Patent Office: Days
• US Class Current: 257/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05683 Rhenium [Re] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and conductive material at both the active surface and the thinned back side. A metal layer having a glass transition temperature greater than that of the solder may be plated to form a dam structure covering one or both ends of the TWI. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

Claims

1. A method for forming through vias in a substrate, comprising:

forming at least one hole in a substrate having an initial thickness between a first surface and an opposing second surface, and extending the at least one hole from the first surface to a depth less than the initial thickness;

passivating at least a sidewall of the at least one hole;

forming a conductive layer within the at least one hole;

forming a vent hole associated with the at least one hole, and extending the vent hole between the second surface and the at least one hole, to at least partially intersect the at least one hole; and

filling the at least one hole with a conductive material.

4. The method of claim 1, wherein forming at least one hole in a substrate comprises forming the at least one hole through a bond pad disposed over the first surface of the substrate.

5. The method of claim 4, wherein forming a conductive layer within the at least one hole comprises electrically coupling the conductive layer to the bond pad.

6. The method of claim 1, wherein passivating at least the sidewalls of the at least one hole comprises forming a passivation layer by one of physical vapor deposition, atomic layer deposition, chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal nitridation, spin-on-glass process, and flow coating.

7. The method of claim 1, wherein forming a conductive layer within the at least one hole comprises:

forming a seed layer within the at least one hole; and

forming a conductive layer over the seed layer within an interior of the at least one hole.

8. The method of claim 1, wherein forming a conductive layer within the at least one hole comprises forming a conductive layer comprising a solder-wetting material.

9. The method of claim 1, wherein forming a vent hole comprises forming the vent hole extending through the passivated sidewall and the conductive layer.

10. The method of claim 1, wherein forming a vent hole comprises forming the vent hole to be coaxial with the at least one hole.

11. The method of claim 1, wherein forming a vent hole comprises forming the vent hole to intersect the at least one hole at an acute angle.

2. The method of claim I, further comprising removing a portion of the initial thickness of the substrate from the second surface to achieve a final thickness, wherein at least enough material is removed to remove the vent hole and expose the conductive material proximate the second surface.

3. The method of claim 2, further comprising attaching at least one conductive cap over the at least one hole to at least one of the first surface and the second surface.

12. A method for forming through vias, comprising:

forming at least one blind hole in a substrate from one surface thereof to a depth less than an initial thickness of the substrate;

forming a passivation layer over at least a sidewall of the at least one blind hole;

forming a layer of a first conductive material within an interior of the at least one blind hole;

forming a vent hole in the substrate to at least partially intersect the at least one blind hole;

disposing a second conductive material within the at least one blind hole;

thinning the substrate to a final thickness, wherein at least the vent hole is removed; and

forming a conductive dam on at least one end of the blind hole.

13. The method of claim 12, further comprising attaching a conductive ball to a surface of the conductive dam.

14. The method of claim 12, wherein forming a passivation layer over at least the sidewall of the at least one blind hole comprises one of oxidating a surface of the sidewall or disposing an electrically insulative material over the surface of the sidewall.

15. The method of claim 12, wherein forming a layer of a first conductive material within the interior of the at least one blind hole comprises:

forming a seed layer within the interior of the at least one blind hole; and

forming a layer of the first conductive material over the seed layer.

16. The method of claim 12, wherein forming a vent hole comprises forming the vent hole to be one of coaxial with the at least one blind hole and at an acute angle with the at least one blind hole.

17. The method of claim 12, wherein forming a conductive dam comprises forming a conductive dam having a glass transition temperature which is higher than the glass transition temperature of the second conductive material.

18. The method of claim 12, wherein attaching a conductive ball to a top surface of the conductive dam comprises attaching a conductive ball having a glass transition temperature lower than the glass transition temperature of the conductive dam.

19. A semiconductor die, comprising:

at least one through via extending from a first surface to a second surface of the semiconductor die, the at least one through via being filled with at least one conductive material; and

at least one dam structure disposed over the at least one through via proximate at least one of the first surface and the second surface.

20. The semiconductor die of claim 19, further comprising a conductive ball electrically coupled to the at least one dam structure.

21. The semiconductor die of claim 20, wherein the at least one dam structure comprises a conductive material having a glass transition temperature which is higher than a glass transition temperature of each of the at least one conductive material and the conductive ball.

22. The semiconductor die of claim 19, wherein the dam structure is electrically connected to a bond pad disposed on a surface of the semiconductor die.

23. An electronic system, comprising a computing device including at least one semiconductor die, the at least one semiconductor die comprising:

at least one through via extending between a first surface and a second surface of the semiconductor die;

at least one conductive material disposed within the at least one through via; and

at least one dam structure extending over the at least one through via on at least one of the first surface and the second surface.