Stacked film patterning method and gate electrode forming method

• US 20070269938A1
• Filed: 05/14/2007
• Published: 11/22/2007
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: NLT Technologies, Ltd.
• Original Assignee: NEC Corporation, NEC LCD Technologies Limited (NEC Corporation)
• Inventors: Hayashi, Kenichi
• Granted Patent: US 7,723,221 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A stacked film patterning method is provided which is capable of reliably removing residual substances remaining after etching of a metal film, improving etching uniformity of a silicon film, and preventing an occurrence of etching residues. A micro-crystal film and a chromium film are sequentially formed on an insulating film serving as a front-end film and the chromium film is etched to be patterned by using a resist as a mask. Next, a micro-crystal silicon film on which the residual substances exist is exposed to plasma of a mixed gas including chlorine gas and oxygen gas to selectively etch the residual substances on a surface of the micro-crystal silicon film. After that, the micro-crystal silicon film is dry etched.

Claims

1. A stacked film patterning method for obtaining a desired stacked film pattern by etching a lower layer film made of a conductive semiconductor and an upper layer film made of metal, said method comprising:

a first etching process of removing a specified region of said upper layer film made of said metal;

a second etching process of removing residues of the metal and/or a compound of the metal with said conductive semiconductor by using plasma of a mixed gas comprising chlorine gas and oxygen gas after completion of said first etching process; and

a third etching process of said lower layer film made of said conductive semiconductor after completion of said second etching process.

2. The stacked film patterning method according to claim 1, wherein said lower layer film is made of polycrystalline silicon or micro-crystal silicon and said upper layer film is made of metal selected from a group consisting of chromium, molybdenum, tungsten, and tantalum or of an alloy comprising said metal.

3. The stacked film patterning method according to claim 1, wherein a ratio of a flow rate of said oxygen gas to said chlorine gas is set to be within a range between 30% and 300%.

4. The stacked film patterning method according to claim 3, wherein said ratio of said flow rate is set to be within a range between 50% and 200%.

5. A stacked film patterning method for obtaining a desired stacked film pattern by etching a stacked film comprising a lower layer film made of a conductive semiconductor and an upper layer film made of metal, said method comprising:

a first etching process of removing a specified region of said upper layer film made of said metal by using a wet-etching method;

a second etching process of removing residues of said metal or a compound of said metal with said conductive semiconductor by using plasma of a mixed gas comprising chlorine gas and oxygen gas after completion of said first etching process; and

a third etching process of removing said lower layer film made of said conductive semiconductor by using a dry-etching method after completion of said second etching process.

6. The stacked film patterning method according to claim 5, wherein said lower layer film is made of polycrystalline silicon or micro-crystal silicon and said upper layer film is made of metal selected from a group consisting of chromium, molybdenum, tungsten, and tantalum or of an alloy comprising said metal.

7. The stacked film patterning method according to claim 5, wherein a ratio of a flow rate of said oxygen gas to said chlorine gas is set to be within a range between 30% and 300%.

8. The stacked film patterning method according to claim 7, wherein said ratio of said flow rate is set to be within a range between 50% and 200%.

9. A gate electrode forming method for obtaining a desired gate electrode pattern by forming a stacked film comprising a lower layer film made of a conductive semiconductor and an upper layer film made of metal on a semiconductor film and gate insulating film deposited sequentially on a substrate and by etching said stacked film, said method comprising:

a first etching process of removing a specified region of said upper layer film made of said metal;

a second etching process of removing residues of said metal or a compound of said metal with said conductive semiconductor by using plasma of a mixed gas comprising chlorine gas and oxygen gas after completion of said first etching process; and

a third process of removing said lower layer film made of said conductive semiconductor after completion of said second etching process.

10. A gate electrode forming method for obtaining a desired gate electrode pattern by forming a stacked film comprising a lower layer film made of a conductive semiconductor and an upper layer film made of metal on a semiconductor film and gate insulating film deposited sequentially on a substrate and by etching said stacked film, said method comprising:

a first etching process of removing a specified region of said upper layer film made of said metal by using a wet-etching method;

a second etching process of removing residues of said metal or a compound of said metal with said conductive semiconductor by using plasma of a mixed gas comprising chlorine gas and oxygen gas after completion of said first etching process; and

a third etching process of removing said lower layer film made of said conductive semiconductor by using a dry-etching method after completion of said second etching process.