Contention-free hierarchical bit line in embedded memory and method thereof

• US 20070280030A1
• Filed: 05/23/2006
• Published: 12/06/2007
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ramaraju, Ravindraraj, Hunter, Bradford D.
• Granted Patent: US 7,440,335 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The bit line driving circuitry further includes a first select input to receive a first select value, a second select input to receive a second select value, and an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.

Claims

1. A memory comprising:

a plurality of lower level bit lines;

a higher level bit line; and

bit line driving circuitry comprising;

a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines;

a first select input to receive a first select value;

a second select input to receive a second select value; and

an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.

2. The memory of claim 1, wherein the lower-level bit lines are local bit lines and the higher level bit line is a global bit line.

3. The memory of claim 1, wherein

the plurality of lower level bit lines comprises a first bit line and a second bit line;

the bit line driving circuitry comprises;

a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of the first select value;

a second transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the first transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a representation of a first bit line value at the first bit line;

a third transistor comprising a first current-carrying electrode coupled to the higher level bit line, a second current-carrying electrode coupled to a second voltage reference, and a control electrode to receive the representation of the first bit line value;

a fourth transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of the second select value;

a fifth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the fourth transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a representation of a second bit line value at the second bit line; and

a sixth transistor comprising a first current-carrying electrode coupled to the higher level bit line, a second current-carrying electrode coupled to the second voltage reference, and a control electrode to receive the representation of the second bit line value.

4. The memory of claim 3, wherein:

the first transistor, the second transistor, the fourth transistor and the fifth transistor are transistors of a first conductivity type; and

the third transistor and the sixth transistor are transistors of a second conductivity type.

5. The memory of claim 3, wherein:

the representation of the first select value is an inverted representation of the first select value;

the representation of the second select value is an inverted representation of the second select value;

the representation of the first bit line value is an inverted representation of the first bit line value; and

the representation of the second bit line value is an inverted representation of the second bit line value;

6. The memory of claim 3, further comprising:

a first inverter comprising an input coupled to the first bit line and an output coupled to the control electrode of the second transistor and coupled to the control gate of the third transistor, the output to provide the inverted representation of the first bit line value;

a second inverter comprising an input coupled to the second bit line and an output coupled to the control electrode of the fifth transistor and coupled to the control electrode of the sixth transistor, the output to provide the inverted representation of the second bit line value;

a seventh transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to the first bit line, and a control electrode coupled to the output of the first inverter, wherein the seventh transistor is a transistor of the first conductivity type; and

an eighth transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to the second bit line, and a control electrode coupled to the output of the second inverter, wherein the eighth transistor is a transistor of the first conductivity type.

7. The memory of claim 1, wherein the bit line coupling component comprises:

a NAND gate comprising a first input coupled to a first bit line of the plurality of lower level bit lines, a second input coupled to a second bit line of the plurality of lower level bit lines, and an output;

a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode, and a control electrode to receive a control value based on an OR logic operation on a representation of the first select value and a representation of the second select value;

a second transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the first transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode coupled to the output of the NAND gate; and

a third transistor comprising a first current-carrying electrode coupled to the second higher level bit line, a second current-carrying electrode coupled to a second voltage reference, and a control electrode coupled to the output of the NAND gate.

8. The memory of claim 7, further comprising:

a NOR gate comprising a first input to receive the first select value, a second input to receive the second select value, and an output coupled to the control electrode of the first transistor.

9. The memory of claim 7, further comprising:

an OR gate comprising a first input to receive the first select value, a second input to receive the second select value, and an output;

an inverter comprising an input coupled to the output of the OR gate and an output coupled to the control electrode of the first transistor; and

a fourth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the third transistor, a second current-carrying electrode coupled to the second voltage reference, and a control electrode to receive a clock signal, wherein the second current-carrying electrode of the third transistor is coupled to the second voltage reference via the fourth transistor.

10. The memory of claim 1, further comprising:

an OR gate comprising a first input to receive the first select value, a second input to receive the second select value, and an output;

an AND gate comprising a first input coupled to the output of the OR gate, a second input to receive a clock signal, and an output;

an inverter comprising an input coupled to the output of the AND gate and an output coupled to the control electrode of the first transistor; and

a fourth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the third transistor, a second current-carrying electrode coupled to the second voltage reference, and a control electrode coupled to the output of the AND gate, wherein the second current-carrying electrode of the third transistor is coupled to the second voltage reference via the fourth transistor.

11. The memory of claim 1, further comprising a transistor comprising a first current-carrying electrode coupled to a voltage reference, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a precharge control value.

12. The memory of claim 1, further comprising:

a first transistor comprising a first current-carrying electrode coupled to a voltage reference, a second current-carrying electrode coupled to a first bit line of the plurality of lower level bit lines, and a control electrode to receive a clock signal; and

a second transistor comprising a first current-carrying electrode coupled to the voltage reference, a second current-carrying electrode coupled to a second bit line of the plurality of lower level bit lines, and a control electrode to receive the clock signal.

13. The memory of claim 1, wherein the first select value is a first bit value of an address predecode value and the second select value is a second bit value of the address predecode value.

14. The memory of claim 1, wherein each of the lower level bit lines is a global bit line of a corresponding memory sector of a plurality of memory sectors and the higher level bit line is a sector bit line.

15. The memory of claim 14, wherein each memory sector comprises:

a fourth bit line;

a fifth bit line;

a sixth bit line;

a seventh bit line;

a first NAND gate comprising a first input coupled to the fourth bit line, a second input coupled to the fifth bit line, and an output;

a second NAND gate comprising a first input coupled to the sixth bit line, a second input coupled to the seventh bit line, and an output;

a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode coupled to the first bit line, and a control electrode coupled to the output of the first NAND gate; and

a second transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to a corresponding global bit line, and a control electrode coupled to the output of the second NAND gate.

16. The memory of claim 15, further comprising:

a third transistor comprising a first current-carrying electrode coupled to a second voltage reference, a second current-carrying electrode coupled to the first bit line, and a control electrode to receive a clock signal.

17. A memory comprising:

a first bit line;

a second bit line;

a third bit line;

a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of a first select value;

a second transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the first transistor, a second current-carrying electrode coupled to the third bit line, and a control electrode coupled to the first bit line;

a third transistor comprising a first current-carrying electrode coupled to the third bit line, a second current-carrying electrode coupled to a second voltage reference, and a control electrode coupled to the first bit line;

a fourth transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode, and a control electrode to receive a second select value;

a fifth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the fourth transistor, a second current-carrying electrode coupled to the third bit line, and a control electrode coupled to the second bit line; and

a sixth transistor comprising a first current-carrying electrode coupled to the third bit line, a second current-carrying electrode coupled to the second voltage reference, and a control electrode coupled to the second bit line.

18. In a memory comprising a first bit line and a second bit line coupled to a third bit line, a method comprising:

receiving a plurality of bit line values, each bit line value from a corresponding lower level bit line of a plurality of lower level bit lines; and

driving a select one of a first bit value or a second bit value onto a higher level bit line based on a first select value associated with a first of the plurality of lower level bit lines and a second select value associated with a second of the plurality of lower level bit lines and based on the first bit line value and the second bit line value.

19. The method of claim 18, wherein driving a select one of the first bit value or the second bit value onto the higher level bit line comprises:

driving the first bit value onto the higher level bit line responsive to the first select value comprising a first value and the second select value comprising a second value, the second value different than the first value; and

driving the second bit value onto the higher level bit line responsive to the first select value comprising the second value and the second select value comprising the first value.

20. The method of claim 18, wherein the first select value is a first bit value of an address predecode value and the second select value is a second bit value of the address predecode value.