DELAY LINE WITH DELAY CELLS HAVING IMPROVED GAIN AND IN BUILT DUTY CYCLE CONTROL AND METHOD THEREOF

• US 20070285144A1
• Filed: 06/10/2007
• Published: 12/13/2007
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: Cosmic Circuits Private Limited
• Original Assignee: Cosmic Circuits Private Limited
• Inventors: BHOWMIK, Prasenjit, KRISHNAN, Sundararajan, Sriram, G.
• Granted Patent: US 7,548,104 B2
• Time in Patent Office: Days
• US Class Current: 327/261
• CPC Class Codes: H03H 11/265 with adjustable delay
• CPC Class Codes: H03K 2005/00045 Dc voltage control of a capacitor or of the coupling of a capacitor as a load
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Claims

1. A delay cell, the delay cell comprising:

a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal;

a first transistor including a drain, a gate, and a source, wherein the drain of the first transistor is electrically connected to the drain of the current source, the gate of the first transistor receives an input clock signal that drives the delay cell, and the source of the first transistor is electrically connected to a power supply terminal;

a second transistor including a drain, a gate, and a source, wherein the drain of the second transistor is electrically connected to the source of the current source, the gate of the second transistor receives the input clock signal, and the source of the second transistor is electrically connected to a ground terminal;

a third transistor including a drain, a gate, and a source, wherein the gate of the third transistor is electrically connected to the drain of the current source, and the source of the third transistor is electrically connected to the power supply terminal;

a fourth transistor including a drain, a gate, and a source, wherein the drain of the fourth transistor is electrically connected to the drain of the third transistor, the gate of the fourth transistor is coupled to an output of an another delay cell, and the source of the fourth transistor is electrically connected to the ground terminal; and

a load capacitor having a first terminal and a second terminal, wherein the first terminal is electrically connected to the drain of the current source, and the second terminal is electrically connected to the ground terminal.

2. The delay cell of claim 1, wherein the first and third transistors are P-type Metal Oxide Semiconductor transistors.

3. The delay cell of claim 1, wherein the second and fourth transistors are N-type Metal Oxide Semiconductor transistors.

4. The delay cell of claim 1, wherein the current source is an N-type Metal Oxide Semiconductor current source transistor.

5. The delay cell of claim 1 further comprising:

a first inverter including an input and an output, wherein the input of the first inverter is coupled to the drain of the third transistor;

a second inverter including an input and an output, wherein the input of the second inverter is coupled to the output of the first inverter, and the output of the second inverter is coupled to the input of the first inverter; and

a third inverter including an input and an output, wherein the input of the third inverter is coupled to the output of the first inverter.

6. The delay cell of claim 5, wherein the first inverter receives a first intermediate clock signal at the input of the first inverter, and generates a second intermediate clock signal in response to the first intermediate clock signal.

7. The delay cell of claim 6, wherein the third inverter generates an output clock signal that is delayed in time with respect to the input clock signal in response to the second intermediate clock signal.

8. A delay line including a sequence of delay cells, a first delay cell of the sequence being driven by a reference clock signal, and each successive delay cell of the sequence being driven by an output from a preceding delay cell, wherein each delay cell of the sequence comprises:

a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal;

a first transistor including a drain, a gate, and a source, wherein the drain of the first transistor is electrically connected to the drain of the current source, the gate of the first transistor receives an input clock signal that drives the delay cell, and the source of the first transistor is electrically connected to a power supply terminal;

a second transistor including a drain, a gate, and a source, wherein the drain of the second transistor is electrically connected to the source of the current source, the gate of the second transistor receives the input clock signal, and the source of the second transistor is electrically connected to a ground terminal;

a third transistor including a drain, a gate, and a source, wherein the gate of the third transistor is electrically connected to the drain of the current source, and the source of the third transistor is electrically connected to the power supply terminal;

a fourth transistor including a drain, a gate, and a source, wherein the drain of the fourth transistor is electrically connected to the drain of the third transistor, the gate of the fourth transistor is coupled to an output of a second consecutive delay cell following the delay cell, and the source of the fourth transistor is electrically connected to the ground terminal; and

a load capacitor having a first terminal and a second terminal, wherein the first terminal is electrically connected to the drain of the current source, and the second terminal is electrically connected to the ground terminal.

9. The delay line of claim 8, wherein the first and third transistors are P-type Metal Oxide Semiconductor transistors.

10. The delay line of claim 8, wherein the second and fourth transistors are N-type Metal Oxide Semiconductor transistors.

11. The delay line of claim 8, wherein the current source is an N-type Metal Oxide Semiconductor current source transistor.

12. The delay line of claim 8, wherein the delay cell further comprises:

a first inverter including an input and an output, wherein the input of the first inverter is coupled to the drain of the third transistor;

a second inverter including an input and an output, wherein the input of the second inverter is coupled to the output of the first inverter, and the output of the second inverter is coupled to the input of the first inverter; and

a third inverter including an input and an output, wherein the input of the third inverter is coupled to the output of the first inverter.

13. The delay line of claim 12, wherein the first inverter receives a first intermediate clock signal at the input of the first inverter, and generates a second intermediate clock signal in response to the first intermediate clock signal.

14. The delay line of claim 13 wherein the third inverter generates an output clock signal that is delayed in time with respect to the input clock signal in response to the second intermediate clock signal.

15. A method for controlling duty cycle, the method comprising:

controlling an edge of an input signal depending on a bias voltage, wherein controlling an edge results in a controlled edge; and

generating an other non-controlled edge of the input signal from the controlled edge with a delay equal to delay value of two identical delay stages.

16. A method for maintaining a gain and a duty cycle of a delay cell, the delay cell comprising a first transistor, a second transistor, a third transistor, a fourth transistor, and a load capacitor, the method comprising:

providing a discharge path for a charge stored in the load capacitor, wherein the discharge path is provided by inserting a current source between a drain of the first transistor and the drain of the second transistor, and wherein the load capacitor discharges to ground through the current source and the second transistor, wherein a source of the current source is electrically connected to the drain of the second transistor; and

providing a pull down path to an intermediate output of the delay cell based on receiving a pulse of an output of a second consecutive delay cell to the delay cell at a gate of the fourth transistor, wherein the intermediate output is received at a junction between the drain of the third transistor and the drain of the fourth transistor, wherein receiving the intermediate output is based on receiving the charge stored in the load capacitor at a gate of the third transistor.

17. A method for improving gain and duty cycle control of a delay cell, the delay cell comprising a first transistor, a second transistor, a third transistor, a fourth transistor, and a load capacitor, the method comprising:

inserting a current source between the first transistor and the second transistor;

providing a voltage bias signal to a gate of the current source;

providing an input clock signal to a gate of the first transistor and a gate of the second transistor;

providing an output of an another delay cell to the ground of the fourth transistor; and

connecting a first terminal of a capacitor to a drain of the current source and a second terminal of the capacitor to a ground terminal.