DIGITAL RECEIVER SYNCHRONIZATION

• US 20070286314A1
• Filed: 05/25/2007
• Published: 12/13/2007
• Est. Priority Date: 05/26/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Herzinger, Stefan, Menkhoff, Andreas, Meier, Stefan, Neurohr, Norbert
• Granted Patent: US 7,912,165 B2
• Time in Patent Office: Days
• US Class Current: 375/343
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Claims

1. A method for synchronizing a receiver including identifying a preamble in a frame, where the preamble has a preamble length 1, comprising:

m data items received in succession are stored;

the m data items are divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n;

m>

n, m>

1, n>

1;

the n portions are respectively correlated to expected values to form component correlation results;

the component correlation results are respectively delayed, with at least two component correlation results being delayed by different lengths;

the delayed component correlation results are combined to form a total correlation value; and

the total correlation value is used to determine whether the m received data items contain the preamble of a frame, for synchronizing the receiver.

2. The method of claim 1, wherein the following additionally applies to m:

m>

1.

3. A method including identifying a preamble in a frame, where the preamble has a preamble length 1, comprising:

m data items received in succession are stored;

the m data items are divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n;

m>

n, m>

1, n>

1;

the n portions are respectively correlated to expected values to form component correlation results;

the component correlation results are respectively delayed, with at least two component correlation results being delayed by different lengths;

the delayed component correlation results are combined to form a total correlation value; and

the total correlation value is used to determine whether the m received data items contain the preamble of a frame.

4. The method of claim 3, wherein the following additionally applies to m:

m>

1.

5. The method of claim 3, wherein the processes of delaying the component correlation results and of combining the component correlation results are performed multiple times, where the process of delaying the component correlation results differ in terms of the length of the delays, and the process of combining the component correlation results involve a multiplicity of total correlation results being produced, and it is established that the m received data items contain the preamble of a frame if at least one of the total correlation results illustrates that the preamble is contained in the m received data items.

6. The method of claim 5, wherein the multiple process of respectively delaying the component correlation results are performed at parallel times and the multiple process of combining the component correlation results are performed at parallel times.

7. The method of claim 5, wherein the process of multiple determination of whether one of the total correlation results illustrates that the preamble is contained in the m received data items are performed at parallel times.

8. The method of claim 3, wherein the following additionally applies to n:

n<

10.

9. The method of claim 3, wherein the following additionally applies to m:

15<

m<

40.

10. The method of claim 3, wherein the difference between the longest and the shortest delay in delaying the component correlation results is greater than 6% of the nominal data rate of the received data items.

11. The method of claim 3, wherein the data items are transmitted wirelessly using a signal which has a frequency in the range from 100 MHz to 1 GHz.

12. A circuit for identifying a preamble having a preamble length 1 in a frame, which has the following:

a memory configured to store m successively received data items;

n component correlators where each component correlator respectively correlates a portion of the data items stored in the memory to expected values and outputs the result of this correlation on an output, and where the respective data items from the portion of the data items have been received in succession;

at least one combiner which combines output signals from a plurality of component correlators, with the output signals from at least two component correlators being delayed by different lengths; and

a decision block which receives at least one output signal from the combiner and indicates whether the preamble is present in the received data items.

13. The circuit of claim 12, comprising wherein m>

1.

14. The circuit of claim 12, comprising wherein the output of each component correlator has a plurality of delay elements connected in series and has a plurality of groups of adders, where each group of adders adds the output signals from delay elements in all the component correlators and the groups of adders differ from one another in that they are connected to the outputs of different delay elements.

15. The circuit of claim 12, comprising wherein the memory storing successively received data items is in the form of a shift register.

16. The circuit of claim 14, comprising wherein the longest delay element delays by at least Z time units longer than the shortest delay element, with Z time units corresponding to 6% of the nominal data rate of the received data items.

17. The circuit of claim 12, comprising wherein n<

10.

18. The circuit of claim 12, comprising wherein the following is true:

15<

m<

40.

19. The circuit of claim 12, comprising wherein the circuit is part of a receiver in a “

keyless go”

system.

20. The circuit of claim 12, comprising where the circuit is integrated in a chip.