PHASE LOCK LOOP AND DIGITAL CONTROL OSCILLATOR THEREOF

• US 20070291173A1
• Filed: 03/29/2007
• Published: 12/20/2007
• Est. Priority Date: 05/24/2006
• Status: Abandoned Application

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Hsin, Don
• Application Number:
  US11/692,930
• Publication Number:
  US 20070291173A1
• Time in Patent Office: Days
• US Class Current: 348/538
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase lock loop including a time-to-digital converter, a period counter, a phase accumulator, a comparator, and an output unit is disclosed. The time-to-digital converter outputs a detected phase error based on the timing difference between a reference clock signal and an output clock signal. The period counter increases a first accumulative value in each period of the output clock signal. The phase accumulator increases a second accumulative value in each period of the reference clock signal and outputs the second accumulative value as an estimative phase error between the reference clock signal and the output clock signal in next period. The comparator outputs a frequency correction signal according to the detected phase error, the first accumulative value, and the estimative phase error. The output unit provides the output clock signal and adjusts its frequency according to the frequency correction signal.

Claims

1. A phase lock loop, comprising:

a time-to-digital converter, outputting a detected phase error according to the timing difference between a reference clock signal and an output clock signal;

a period counter, storing and outputting a first accumulative value, adding 1 to the first accumulative value in each period of the output clock signal;

a phase accumulator, storing a second accumulative value, adding N to the second accumulative value in each period of the reference clock signal, outputting an estimative phase error according to the second accumulative value, wherein N is a real number greater than 0;

a comparator, outputting a frequency correction signal according to the detected phase error, the first accumulative value, and the estimative phase error; and

an output unit, providing the output clock signal, adjusting the frequency of the output clock signal according to the frequency correction signal.

2. The phase lock loop as claimed in claim 1, wherein the time-to-digital converter comprises:

a plurality of buffers, wherein the first buffer receives the reference clock signal, and each of the other buffers receives the output of the previous buffer;

a sampler, capturing the output of the buffers based on the output clock signal; and

an encoder, producing the detected phase error according to the sampling result of the sampler.

3. The phase lock loop as claimed in claim 1, wherein the estimative phase error is the fractional part of the second accumulative value.

4. The phase lock loop as claimed in claim 1, wherein the output unit comprises:

a loop filter, adjusting and outputting a frequency control value according to the frequency correction signal, the frequency control value being an analog voltage; and

a voltage control oscillator, generating the output clock signal according to the frequency control value.

5. The phase lock loop as claimed in claim 1, wherein the output unit comprises:

a bi-directional counter, adjusting and outputting a frequency control value according to the frequency correction signal, the frequency control value being a digital signal; and

a digital control oscillator, generating the output clock signal according to the frequency control value.

6. The phase lock loop as claimed in claim 5, wherein the bi-directional counter increases the frequency control value when the frequency correction signal is in a first state, and decreases the frequency control value when the frequency correction signal is in a second state.

7. The phase lock loop as claimed in claim 5, wherein the digital control oscillator comprises:

an inverter, receiving the output clock signal, outputting the inverted and delayed output clock signal to the output terminal of the digital control oscillator; and

a delay module, receiving the output clock signal from the inverter, delaying the output clock signal a period of time and then outputting the delayed output clock signal to the inverter, the delay time period being determined according to the frequency control value.

8. The phase lock loop as claimed in claim 7, wherein the delay module comprises:

a plurality of buffers, wherein the first buffer receives the output clock signal from the inverter, and each of the other buffers receives the output of the previous buffer; and

a selector, providing the output of one of the buffers to the inverter according to the frequency control value.

9. The phase lock loop as claimed in claim 7, wherein the digital control oscillator further comprises:

a dithering unit, providing a frequency dithering value to the selector according to the frequency control value and a predetermined rule to select the output of the buffers based on the frequency dithering value, wherein the effective bit number of the frequency dithering value is smaller than the effective bit number of the frequency control value, and the average value of the frequency dithering value within a predetermined period is equal to the frequency control value.

10. The phase lock loop as claimed in claim 9, wherein the dithering unit comprises:

a dithering accumulator, storing a third accumulative value, adding the frequency control value to the third accumulative value in each period of a clock signal; and

the frequency dithering value being one of A and B, A>

B, the dithering unit outputting A as the frequency dithering value if the additive operation of the third accumulative value produces carry, otherwise the dithering unit outputting B as the frequency dithering value.

11. The phase lock loop as claimed in claim 10, wherein A is equal to B+1.

12. A digital control oscillator, comprising:

a dithering unit, providing a frequency dithering value according to a frequency control value and a predetermined rule, wherein the effective bit number of the frequency dithering value is smaller than the effective bit number of the frequency control value, and the average value of the frequency dithering value during a predetermined period is equal to the frequency control value;

an inverter, receiving an output clock signal, outputting the inverted and delayed output clock signal to the output terminal of the digital control oscillator; and

a delay module, receiving the output clock signal from the inverter, delaying the output clock signal a period of time and then outputting the delayed output clock signal to the inverter, the delaying time period being determined according to the frequency dithering value.

13. The digital control oscillator as claimed in claim 12, wherein the dithering unit comprises:

a dithering accumulator, storing an accumulative value, adding the frequency control value to the accumulative value in each period of a clock signal; and

the frequency dithering value being one of A and B, A>

B, the dithering unit outputting A as the frequency dithering value if the additive operation of the accumulative value produces carry, otherwise the dithering unit outputting B as the frequency dithering value.

14. The digital control oscillator as claimed in claim 13, wherein A is equal to B+1.

15. The digital control oscillator as claimed in claim 12, wherein the delay module comprises:

a plurality of buffers, wherein the first buffer receives the output clock signal from the inverter, and each of the other buffers receives the output of the previous buffer; and

a selector, providing the output of one of the buffers to the inverter according to the frequency dithering value.