Watchdog processors in multicore systems

• US 20070294601A1
• Filed: 05/19/2006
• Published: 12/20/2007
• Est. Priority Date: 05/19/2006
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Chitsaz, Behrooz, Kirovski, Darko
• Granted Patent: US 7,958,396 B2
• Time in Patent Office: Days
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 2221/2101 Auditing as a secondary aspect

Abstract

Systems and methods are provided for securing a multicore computer chip with a watchdog processor. In a system with a watchdog process and any number of other processors and components, the watchdog processor monitors bus communications between the second processor and at least one third component. The watchdog processor may be further independently coupled to at least one of the other components so that it can monitor internal operations of such component, thereby acquiring detailed information about the specific operations of at least one component in the system. The watchdog processor can enforce an interaction policy on bus communications between components, as well as enforce an independent security policy on the monitored components.

Claims

1. A system comprising:

a first processor;

a second processor;

at least one third component;

a bus between said second processor and said at least one third component, wherein the first processor is configured to monitor activity on said bus;

at least one wire connection between said first processor and said second processor, wherein said wire connection is independent of said bus, and wherein said first processor can monitor an internal component of said second processor via said wire connection.

2. The system of claim 1, wherein said first, second, and at least one third component are located on a single computer chip.

3. The system of claim 1, wherein said internal component of said second processor is a register.

4. The system of claim 1, wherein said internal component of said second processor is a stack pointer table.

5. The system of claim 1, wherein said first processor enforces a policy on said second processor.

6. The system of claim 1, wherein said at least one third component comprises a processor.

7. The system of claim 1, further comprising at least one wire connection between said first processor and said at least one third component.

8. A system comprising:

a first processor;

a second processor electrically coupled to said first processor;

a software application comprising a set of application functions and a processor policy, wherein said set of application functions are executed by said second processor, and wherein said processor policy is enforced against said second processor by said first processor.

9. The system of claim 8, wherein said first processor and said second processor are configured such that the first processor can halt a process running on said second processor.

10. The system of claim 8, wherein said first and second processor are located on a single computer chip.

11. The system of claim 8, wherein said processor policy detects a system call that launches a command shell.

12. The system of claim 8, wherein said processor policy detects if a child process is started on said second processor.

13. The system of claim 8, wherein said processor policy identifies a plurality of legal jump instructions.

14. The system of claim 8, wherein said processor policy identifies a plurality of legal call instructions.

15. The system of claim 8, wherein said processor policy identifies a read access to uninitialized memory.

16. The system of claim 8, further comprising at least one wire connection between said first processor and at least one third component, wherein said first processor can monitor information in an internal component of said at least one third component via said wire connection.

17. The system of claim 8, wherein said processor policy is a dynamically evolving processor policy.

18. A system comprising:

a first processor electronically coupled to a bus, and configured to monitor the interaction of a second processor and a third processor, wherein said first processor is configured to enforce an interaction policy against said second processor and third processor;

wherein said second processor is electronically coupled to said third processor via said bus; and

wherein said second processor is configured to initiate at least one process on said third processor.

19. The system of claim 18, wherein said processor policy is a dynamically evolving processor policy.

20. The system of claim 18, wherein said dynamically evolving processor policy identifies normal behavior and/or abnormal behavior of one or more of said second and said third processor.