Techniques for hardware-assisted multi-threaded processing

• US 20070294694A1
• Filed: 06/16/2006
• Published: 12/20/2007
• Est. Priority Date: 06/16/2006
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Jeter, Robert, Gamer, Trevor, Lee, William, Smith, Scott, Goss, Gegory
• Granted Patent: US 8,041,929 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2^c registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2^T threads. A particular register is accessed in a register bank that has 2^(C+T) registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.

Claims

1. An apparatus for processing a thread of a plurality of threads that share a core processor, comprising:

an instruction random access memory (IRAM) for storing one or more sequences of instructions;

a bank of registers for storing data that is used as operands and results of the one or more series of instructions for a plurality of threads, said bank of registers including a bank address input for accessing a register in the bank of registers;

a thread ID input channel that has a width of T bits for receiving data that indicates a current thread identifier (ID) of a plurality of up to 2^T threads, said thread ID input channel connected to T bits of the bank address input; and

a core processor for executing the one or more sequences of instructions for a current thread of the plurality of threads by accessing contents of a register for up to 2^c registers for the current thread in the bank of registers; and

a core register access channel with a width of C bits, which connects the core processor to C bits of the bank address input different from the T bits to which the thread ID input channel is connected,

wherein.

the bank of registers includes 2^(C+T) registers,

the bank address input includes a number C+T bits, and

an intra-thread register indicated by the core processor has an intra-thread address that has C bits,

whereby, for a particular intra-thread register indicated on the core register access channel, a particular register accessed by the bank address input holds data that indicates contents for the particular intra-thread register for a thread having the current thread ID,

2. An apparatus as recited in claim 1, wherein:

the apparatus further comprises

a data random access memory (data RAM) for storing additional data for the plurality of threads, said data RAM including a data RAM address input for accessing contents of a location in the data RAM, and

a core data RAM channel with a width of D bits, which connects the core processor to D bits of the data RAM address input;

the thread input channel is connected to T bits of the data RAM address input different from the D bits to which the core data RAM channel is connected, and

an intra-thread data RAM address indicated by the core processor has an intra-thread data RAM address that has D bits.

3. An apparatus as recited in claim 1, further comprising a switch output channel from the core processor, wherein the one or more sequences of instructions include instructions that, when executed by the core processor cause the core processor to send a thread switch signal on the switch output channel during a cycle when a current thread relinquishes control of the core processor.

4. An apparatus as recited in claim 3, further comprising a flip-flop register connected to the switch output channel and the thread ID input channel, wherein the apparatus is configured such that:

the flip flop register holds data that indicates a thread ID of a next thread to execute on the core processor; and

when the thread switch signal is received at the flip-flop register, the data that indicates the thread ID of the next thread is placed on the thread ID input channel.

5. An apparatus as recited in claim 4, further comprising a thread scheduler block different from the core processor, wherein the thread scheduler block is configured to perform the step of sending, to the flip-flop register, the data that indicates the thread ID of the next thread.

6. An apparatus as recited in claim 5, wherein the thread scheduler block is further configured to perform the steps of:

receiving thread instruction location data from the core processor when a thread is ready to relinquish control of the core processor, which thread instruction location data indicates a location in the IRAM where the thread is to resume when switched back onto the core processor; and

sending thread instruction location data to the core processor for the next thread.

7. An apparatus as recited in claim 5, wherein the thread scheduler block is further configured to perform the step of determining which thread, if any, of a plurality of threads switched off the core processor is the next thread.

8. An apparatus as recited in claim 5, wherein.

the apparatus further comprises a switch preparation channel connecting the core processor to the thread scheduler;

execution of the one or more sequences of instructions by the core processor further causes the core processor to perform the step of sending a prepare-to-switch signal on the switch preparation channel before said step of sending a thread switch signal; and

the thread scheduler block is further configured to perform the steps of

receiving the prepare-to-switch signal on the switch preparation channel, and

performing said step of sending, to the flip-flop register, the data that indicates the thread ID of the next thread in response to receiving the prepare-to-switch signal.

9. An apparatus as recited in claim 8, wherein. the thread scheduler block is further configured to perform the step of determining which thread, if any, of a plurality of threads that were previously switched off the core processor is the next thread, in response to receiving the prepare-to-switch signal.

10. An apparatus as recited in claim 8, wherein

the apparatus further comprises a thread instruction channel connecting the core processor to the thread scheduler;

the prepare-to-switch signal includes data that indicates, for the current thread, thread instruction location data that indicates a location in the IRAM where a thread is to resume when switched back onto the core processor; and

the thread scheduler block is further configured to perform the step of sending thread instruction location data for the next thread to the core processor over the thread instruction channel in response to receiving the prepare-to-switch signal.

11. An apparatus as recited in claim 1, further comprising a network interface for communicating there through a data packet.

12. A method for processing a thread of a plurality of threads that share a core processor, comprising the steps of:

receiving, from a core processor, a intra-thread register address that contains a core number C of bits for accessing each register of 2^C registers available to each thread of a plurality of threads;

receiving, from a thread scheduler component external to the core processor, a thread identifier (ID) that contains a thread ID number T of bits for indicating a particular thread in a plurality of up to 2^T threads; and

accessing, in a computer-readable medium configured as register bank that has 2^(C+T) registers, a particular register that has an inter-thread address that includes both the intra-thread register address and the thread ID,

wherein the particular register holds data that indicates contents for the intra-thread register address for a thread having the thread ID,

whereby register contents of all registers of all threads reside in the register bank.

13. A method as recited in claim 12, wherein the thread ID received from the thread scheduler component indicates a current thread executing on the core processor.

14. A method as recited in claim 12, further comprising the steps of:

receiving, from a core processor, a intra-thread data random access memory (data RAM) address that contains a core data number D of bits for accessing each data RAM address of 2^D data RAM addresses available to each thread of the plurality of threads;

receiving, from the thread scheduler component, the thread ID; and

accessing, in a computer-readable medium configured as a data RAM that has 2^(D+T) locations, a particular data RAM location that has an inter-thread data RAM address that includes both the intra-thread data RAM address and the thread ID,

wherein the particular data RAM location holds data that indicates contents for the intra-thread data RAM address for a thread having the thread ID,

whereby data RAM contents of all intra-thread data RAM addresses of all threads reside in the data RAM.

15. A method as recited in claim 12, further comprising the steps of:

sending a thread switch signal during a cycle when a current thread relinquishes control of the core processor; and

receiving a new thread ID for a next thread of the plurality of threads in response to sending the thread switch signal.

16. A method as recited in claim 15, further comprising the steps of:

receiving thread instruction location data when a thread is ready to relinquish control of the core processor, which thread instruction location data indicates a location in a computer-readable medium configured as an instruction random access memory (IRAM) where the thread is to resume when switched back onto the core processor; and

sending thread instruction location data to the core processor for the next thread.

17. A method as recited in claim 15, further comprising the step of determining which thread, if any, of a plurality of threads switched off the core processor is the next thread.

18. A method as recited in claim 15, further comprising the steps of:

sending a prepare-to-switch signal before said step of sending a thread switch signal; and

performing said step of sending the data that indicates the thread ID of the next thread in response to receiving the prepare-to-switch signal.

19. A method as recited in claim 18, further comprising the steps of determining which thread, if any, of a plurality of threads that were previously switched off the core processor is the next thread, in response to receiving the prepare-to-switch signal.

20. A method as recited in claim 18, wherein:

the prepare-to-switch signal includes data that indicates, for the current thread, thread instruction location data that indicates a location in the IRAM where a thread is to resume when switched back onto the core processor; and

the method further comprises the step of sending thread instruction location data for the next thread to the core processor in response to receiving the prepare-to-switch signal.

21. An apparatus for processing a thread of a plurality of threads that share a core processor, comprising:

means for receiving, from a core processor, a intra-thread register address that contains a core number C of bits for accessing each register of 2^C registers available to each thread of a plurality of threads;

means for receiving, from a thread scheduler component external to the core processor, a thread identifier (ID) that contains a thread ID number T of bits for indicating a particular thread in a plurality of up to 2^T threads; and

means for accessing, in a computer-readable medium configured as register bank that has 2^(C+T) registers, a particular register that has an inter-thread address that includes both the intra-thread register address and the thread ID,

wherein the particular register holds data that indicates contents for the intra-thread register address for a thread having the thread ID,

whereby register contents of all registers of all threads reside in the register bank.

22. A method at a core processor for switching between threads of a plurality of processing threads that share the core processor, comprising the steps of:

sending a prepare-to-switch signal to a first block external to the core processor while executing instructions of a current processing thread, wherein the prepare-to-switch signal includes data that that indicates a current thread revival instruction location in a computer-readable medium configured as an instruction random access memory (IRAM);

, where is located an instruction to be executed by the core processor when the current processing thread resumes processing on the core processor;

in response to sending the prepare-to-switch signal, receiving from the first block a next thread instruction location in the IRAM, where is located an instruction to be executed by the core processor when the next processing thread resumes processing on the core processor; and

after sending the prepare-to-switch signal, performing the steps of

sending a thread switch signal to a second block external to the core processor; and

retrieving a next instruction from the next thread instruction location in the IRAM.

23. A method as recited in claim 22, further comprising the step of accessing a register in a computer-readable medium configured as a bank of registers for up to 2^C registers for each thread of a plurality of 2^T threads that share the core processor by sending C bits from the next instruction to a bank input for the bank of registers, wherein:

the bank of registers includes 2^(C+T) addressable registers each accessed based on C+T bits received at the bank input; and

in response to said step of sending the switch thread signal, T bits that indicate a thread identifier (ID) for the next processing thread are provided to bits in the bank input different from the C bits sent by the core processor.

24. A method as recited in claim 23, wherein the thread ID for the next processing thread is determined by the first block in response to receiving the prepare-to-switch signal.

25. A method as recited in claim 24, wherein:

the second block is different from the first block; and

the thread ID for the next processing block is sent from the first block to the second block in response to receiving the prepare-to-switch signal.

26. A method as recited in claim 22, further comprising the step of accessing a data location in a computer-readable medium configured as a data random access memory (data RAM) for up to 2^D registers for each thread of the plurality of 2^T threads that share the core processor by sending D bits from the next instruction to a data RAM input for the data RAM, wherein:

the data RAM includes 2^(D+T) addressable locations each accessed based on D+T bits received at the data RAM input; and

in response to said step of sending the switch thread signal, T bits that indicate the thread ID for the next processing thread are provided to bits in the data RAM input different from the D bits sent by the core processor.

27. A method as recited in claim 22, further comprising the step of issuing a request for a long-latency memory operation, wherein said step of sending the prepare-to-switch signal to the first block is performed after said step of issuing the request for a long-latency memory operation.

28. A method at a thread scheduler external to a core processor for switching between threads of a plurality of processing threads that share the core processor, comprising the steps of:

receiving a prepare-to-switch signal from a core processor while the core processor executes instructions of a current processing thread, wherein the prepare-to-switch signal includes data that that indicates a current thread revival instruction location in a computer-readable medium configured as an instruction random access memory (IRAM);

, where is located an instruction to be executed by the core processor when the current processing thread resumes processing on the core processor;

storing the current thread revival instruction location in association with a thread ID for the current processing thread in a data structure for a plurality of up to 2^T processing threads that share the core processor; and

in response to receiving the prepare-to-switch signal, performing the steps of

determining a next processing thread of the plurality of up to 2^T processing threads to be executed on the core processor,

retrieving from the data structure a next thread instruction location in the IRAM, where is located an instruction to be executed by the core processor when the next processing thread resumes processing on the core processor, and

sending the next thread instruction location to the core processor.

29. A method as recited in claim 28, further comprising, in response to receiving the prepare-to-switch signal, performing the step of providing the thread ID for the next processing thread for use by a computer-readable medium configured as a bank of registers for up to 2^C registers for each thread, wherein the bank of registers includes 2^(C+T) addressable registers each accessed by C+T bits received at a bank input.

30. A method as recited in claim 29, wherein:

the method further comprises causing the thread ID to be sent to T bits in the bank input in response to a thread switch signal sent from the core processor; and

C bits in the bank input different from the T bits caused to be sent by the thread scheduler are sent by the core processor.

31. A method as recited in claim 28, further comprising, in response to receiving the prepare-to-switch signal, performing the step of providing the thread ID for the next processing thread for use by a computer-readable medium configured as a data random access memory (data RAM) for up to 2^D registers for each thread, wherein the data RAM includes 2^(D+T) addressable registers each accessed by D+T bits received at a data RAM input.

32. A computer-readable medium carrying one or more sequences of instructions for switching between threads of a plurality of processing threads that share a core processor, wherein execution of the one or more sequences of instructions by the core processor causes the core processor to perform the steps of:

sending a prepare-to-switch signal to a first block external to the core processor while executing instructions of a current processing thread, wherein the prepare-to-switch signal includes data that that indicates a current thread revival instruction location in a computer-readable medium configured as an instruction random access memory (IRAM);

, where is located an instruction to be executed by the core processor when the current processing thread resumes processing on the core processor;

in response to sending the prepare-to-switch signal, receiving from the first block a next thread instruction location in the IRAM, where is located an instruction to be executed by the core processor when the next processing thread resumes processing on the core processor; and

after sending the prepare-to-switch signal, performing the steps of

sending a thread switch signal to a second block external to the core processor; and

retrieving a next instruction from the next thread instruction location in the IRAM.