PICK-UP STRUCTURE FOR DRAM CAPACITORS AND DRAM PROCESS

• US 20070296010A1
• Filed: 06/27/2006
• Published: 12/27/2007
• Est. Priority Date: 06/27/2006
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Su, Yi-Nan, Yang, Chin-Sheng
• Granted Patent: US 7,554,148 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the surfaces of the substrate and the trenches, and then a patterned photoresist layer is formed on the conductive layer filling in the trenches and further covering the first trench. The exposed conductive layer is removed to form bottom electrodes in the trenches, and then the patterned photoresist layer is removed. A capacitor dielectric layer is formed on each bottom electrode, and then top electrodes are formed on the substrate filling up the trenches. A contact is then formed on the bottom electrode in the first trench, electrically connecting the substrate via the bottom electrode.

Claims

1. A DRAM process, comprising:

providing a substrate with a plurality of trenches therein, the trenches including a first trench and each trench having a dielectric layer on a sidewall thereof;

forming a conductive layer on surfaces of the substrate and the trenches;

forming a patterned photoresist layer on the conductive layer, the patterned photoresist layer filling in the trenches and further covering the first trench;

removing the exposed conductive layer to form a plurality of bottom electrodes in the trenches;

removing the patterned photoresist layer;

forming a capacitor dielectric layer on each of the bottom electrodes;

forming a plurality of top electrodes over the substrate filling up the trenches; and

forming a contact on the bottom electrode in the first trench, the contact electrically connects with the substrate via the bottom electrode in the first trench.

2. The DRAM process of claim 1, wherein the first trench is at an edge or a corner of a memory cell array area of the DRAM.

3. The DRAM process of claim 1, wherein a top surface of the photoresist layer in each of the trenches other than the first trench is lower than a top surface of the substrate.

4. The DRAM process of claim 1, wherein the trenches include a plurality of pairs of adjacent trenches, further comprising forming two transistors on the substrate beside each pair of adjacent trenches after the top electrodes are formed but before the contact is formed.

5. The DRAM process of claim 4, further comprising forming an isolation structure between each pair of trenches after the top electrodes are formed but before the transistors are formed, the isolation structure encroaching upon the pair of trenches.

6. The DRAM process of claim 5, further comprising forming passing gate structures on the isolation structure during the formation of the transistors.

7. The DRAM process of claim 1, wherein the capacitor dielectric layer comprises an ONO layer.

8. The DRAM process of claim 1, further comprising a surface treatment to bottoms of the trenches having the dielectric layer therein before the conductive layer is formed.

9. The DRAM process of claim 1, further comprising forming a doped band in the substrate through dopant diffusion from bottoms of the trenches.

10. The DRAM process of claim 9, wherein a source of the dopant diffusion includes at least one of an ion implantation conducted to the bottoms of the trenches before the conductive layer is formed and a doped semiconductor material that constitutes the conductive layer.

11. The DRAM process of claim 10, wherein the doped semiconductor material includes doped poly-Si.

12. The DRAM process of claim 10, further comprising conducting an annealing treatment to cause dopant diffusion after the conductive layer is formed.

13. A DRAM process, comprising:

providing a substrate with a plurality of trenches therein, the trenches including a first trench and each trench having a dielectric layer on a sidewall thereof;

forming a bottom electrode on an internal surface of each trench;

forming a capacitor dielectric layer on each bottom electrode;

removing the capacitor dielectric layer in the first trench;

forming a plurality of top electrodes on the substrate filling up the trenches; and

forming a contact on the top electrode in the first trench, electrically connecting with the substrate via the top electrode and the bottom electrode in the first trench.

14. The DRAM process of claim 13, wherein the first trench is at an edge or a cornet of a memory cell array area of the DRAM.

15. The DRAM process of claim 13, wherein a top surface of the bottom electrode in each of the trenches is lower than a top surface of the substrate.

16. The DRAM process of claim 13, wherein the trenches include a plurality of pairs of adjacent trenches, further comprising forming two transistors on the substrate beside each pair of adjacent trenches after the top electrodes are formed but before the contact is formed.

17. The DRAM process of claim 16, further comprising forming an isolation structure between each pair of trenches after the top electrodes are formed but before the transistors are formed, the isolation structure encroaching upon the pair of trenches.

18. The DRAM process of claim 17, further comprising forming passing gate structures on the isolation structure during the formation of the transistors.

19. The DRAM process of claim 13, wherein the capacitor dielectric layer comprises an ONO layer.

20. The DRAM process of claim 13, further comprising conducting a surface treatment to bottoms of the trenches having the dielectric layer therein.

21. The DRAM process of claim 13, further comprising forming a doped band in the substrate through dopant diffusion from bottoms of the trenches.

22. The DRAM process of claim 21, wherein a source of the dopant diffusion includes at least one of an ion implantation conducted to the bottoms of the trenches before the conductive layer is formed and a doped semiconductor material that constitutes the conductive layer.

23. The DRAM process of claim 22, wherein the doped semiconductor material includes doped poly-Si.

24. The DRAM process of claim 22, further comprising conducting an annealing treatment after the conductive layer is formed to cause the dopant diffusion.

25. A capacitor pick-up structure, applied to a memory cell array area of DRAM that is disposed on a substrate over a doped band in the substrate, and comprising:

a dummy capacitor in a first trench in the substrate, wherein a bottom of the first trench exposes a portion of the doped band, the dummy capacitor comprising;

a first bottom electrode on an internal surface of the first trench, electrically connecting with the doped band;

a first dielectric layer between the first bottom electrode and a sidewall of the first trench; and

a first top electrode on the first bottom electrode, filling up the first trench; and

a contact on the dummy capacitor, electrically connecting with the doped band via the dummy capacitor.

26. The capacitor pick-up structure of claim 25, which is disposed at an edge of the memory cell array area.

27. The capacitor pick-up structure of claim 25, which is disposed at a corner of the memory cell array area.

28. The capacitor pick-up structure of claim 25, wherein a top surface of the first bottom electrode is higher than or coplanar with a top surface of the substrate.

29. The capacitor pick-up structure of claim 28, wherein the contact electrically connects with the first bottom electrode at least.

30. The capacitor pick-up structure of claim 28, further comprising a first capacitor dielectric layer between the first bottom electrode and the first top electrode.

31. The capacitor pick-up structure of claim 30, wherein the first capacitor dielectric layer comprises an ONO layer.

32. The capacitor pick-up structure of claim 25, wherein a top surface of the first bottom electrode is lower than a top surface of the substrate.

33. The capacitor pick-up structure of claim 32, wherein the contact is disposed on the first top electrode.

34. The capacitor pick-up structure of claim 25, wherein a memory cell in the memory cell array area comprises:

a transistor on the substrate;

a trench capacitor in the substrate beside the transistor; and

a conductive layer on the substrate for coupling the transistor with the trench capacitor.

35. The capacitor pick-up structure of claim 34, wherein the trench capacitor is disposed in a second trench in the substrate, a bottom of the second trench exposes a portion of the doped band, and the trench capacitor comprises:

a second bottom electrode on an internal surface of the second trench, electrically connecting with the doped band;

a second dielectric layer between the second bottom electrode and a sidewall of the second trench;

a second top electrode on the second bottom electrode, filling up the second trench; and

a second capacitor dielectric layer between the second bottom electrode and the second top electrode.

36. The capacitor pick-up structure of claim 34, wherein the DRAM further comprises an isolation structure that has a portion disposed between every two adjacent trench capacitors and encroaching upon the two adjacent trench capacitors.

37. The capacitor pick-up structure of claim 36, wherein the DRAM further comprises passing gate structures on the isolation structure.

38. The capacitor pick-up structure of claim 25, further comprising an isolation structure that encroaches upon the dummy capacitor.

39. The capacitor pick-up structure of claim 38, wherein the DRAM further comprises a passing gate structure on the isolation structure that encroaches upon the dummy capacitor.