Semiconductor Device, Wiring Board, And Manufacturing Method Thereof

• US 20080001309A1
• Filed: 05/18/2005
• Published: 01/03/2008
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Tago, Masamoto
• Granted Patent: US 7,525,189 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A wiring board (20) includes a first wiring portion (10) having a plurality of wiring layers (1) and a plurality of external connecting bumps (5), and a second wiring portion (15) integrated with the first wiring portion in the direction of thickness. The thermal expansion coefficient of the second wiring portion is made smaller than that of the first wiring portion, and equal to that of a semiconductor chip (30) to be mounted on the wiring board. This suppresses the internal stress resulting from the thermal expansion coefficient difference between the semiconductor chip and wiring board, and increases the reliability of a semiconductor device (50) obtained by mounting the semiconductor chip on the wiring board. The sizes of the opposing surfaces of the first and second wiring portions are also made equal. This requires only one second wiring portion to be formed even when improving the performance of the semiconductor device by mounting a plurality of semiconductor chips on the wiring board, thereby improving the performance at a low cost.

Claims

1. A semiconductor device characterized by comprising:

a wiring board comprising a plurality of connecting terminals arranged on one surface in a direction of thickness and a plurality of external connecting bumps arranged on the other surface in the direction of thickness; and

at least one semiconductor chip connected to said connecting terminals,

wherein said wiring board comprises;

a first wiring portion comprising a plurality of wiring layers and said external connecting bumps; and

a second wiring portion electrically connected to said first wiring portion and integrated with said first wiring portion in the direction of thickness,

said connecting terminals are made of contact plugs formed in through holes extending through the second wiring portion in the direction of thickness,

sizes of opposing surfaces of said first wiring portion and said second wiring portion are equal,

a thermal expansion coefficient of said second wiring portion is smaller than a thermal expansion coefficient of said first wiring portion and equal to a thermal expansion coefficient of said semiconductor chip,

said semiconductor chip is a silicon chip,

said second wiring portion comprises a base made of silicon, and

said contact plugs are formed in said base.

5. A semiconductor device according to claim 1, characterized by further comprising a functional element formed on said second wiring portion which faces said first wiring portion.

6. A semiconductor device according to claim 5, characterized in that said functional element is formed by a thin-film process.

2. (canceled)

3. (canceled)

4. (canceled)

7. A wiring board characterized by comprising:

a first wiring portion comprising a plurality of wiring layers and a plurality of external connecting bumps; and

a second wiring portion comprising a plurality of connecting terminals configured to connect to at least one semiconductor chip,

wherein said second wiring portion is electrically connected to said first wiring portion and integrated with said first wiring portion in a direction of thickness,

said connecting terminals are made of contact plugs formed in through holes extending through said second wiring portion in the direction of thickness,

sizes of opposing surfaces of said first wiring portion and said second wiring portion are equal,

a thermal expansion coefficient of said second wiring portion is smaller than a thermal expansion coefficient of said first wiring portion and equal to a thermal expansion coefficient of said semiconductor chip,

said second wiring portion comprises a base made of silicon, and

said contact plugs are formed in said base.

11. A wiring board according to claim 7, characterized by further comprising a functional element formed on said second wiring portion which faces said first wiring portion.

12. A wiring board according to claim 11, characterized in that said functional element is formed by a thin-film process.

8. (canceled)

9. (canceled)

10. (canceled)

13. A wiring board manufacturing method characterized by comprising the steps of:

forming a first wiring portion comprising a plurality of wiring layers and a plurality of external connecting bumps; and

forming a second wiring portion comprising a plurality of connecting terminals configured to connect to at least one semiconductor chip, such that the second wiring portion is integrated with the first wiring portion in a direction of thickness,

wherein the connecting terminals are made of contact plugs formed in through holes extending through the second wiring portion in the direction of thickness,

sizes of opposing surfaces of the first wiring portion and the second wiring portion are equal,

a thermal expansion coefficient of the second wiring portion is smaller than a thermal expansion coefficient of the first wiring portion and equal to a thermal expansion coefficient of the semiconductor chip,

the step of forming the first wiring portion comprises the step of forming at least a portion of the first wiring portion on one surface in the direction of thickness of a silicon base of the second wiring portion, and

the step of forming the second wiring portion comprises the steps of;

forming a plurality of recesses in said one surface of the base;

burying a conductive material in the recesses; and

after the step of forming at least a portion of the first wiring portion, thinning the base from the other surface in the direction of thickness of the base to expose the conductive material buried in the recesses, thereby forming the contact plugs and obtaining the second wiring portion.

17. A wiring board manufacturing method according to claim 13, characterized by further comprising the step of forming a functional element on a surface in which the recesses are formed, before the steps of burying the conductive material in the recesses and forming at least a portion of the first wiring portion.

18. A wiring board manufacturing method according to claim 17, characterized in that the step of forming the functional element comprises the step of forming the functional element by a thin-film process.

14. (canceled)

15. (canceled)

16. (canceled)