FLEXIBLE METHOD FOR PROCESSING DATA PACKETS IN A NETWORK ROUTING SYSTEM FOR ENHANCED EFFICIENCY AND MONITORING CAPABILITY

• US 20080002707A1
• Filed: 09/12/2007
• Published: 01/03/2008
• Est. Priority Date: 05/06/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks LLC (Broadcom, Inc.)
• Inventors: Davis, Ian
• Granted Patent: US 7,830,884 B2
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 45/16 Multipoint routing
• CPC Class Codes: H04L 45/302 Route determination based on requested QoS
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/2408 for supporting different services, e.g. a differentiated services [DiffServ] type of service
• CPC Class Codes: H04L 47/39 Credit based

Abstract

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

Claims

1-27. -27. (canceled)

28. A data packet processor, comprising:

An input port for receiving data packets;

a microprocessor for processing packet information from the data packets, the microprocessor comprising;

a plurality of registers each assigned to store packet information of the data packets;

an arithmetic logic unit, configured to perform an arithmetic or logic operation on one or more operands to provide a result of the operation, wherein the operation is selected from the group consisting of an inline rotate operation and a mask operation;

a register select circuit, configured to select the content of a selected one of registers as one of the operands; and

a feedback select circuit, configured to provide the result of the operation as one of the operands.

29. A data processor as in claim 28, wherein the microprocessor comprises a RISC processor.

30. A data processor as in claim 28, wherein the arithmetic logic unit can is configured also to perform any one of an and operation, an or operation, an xor operation, a neg operation, an add operation, and a compare operation.

31. A data packet processor as in claim 28, further comprising a content-addressable memory (CAM) lookup handler receiving the contents of the registers, the CAM lookup handler configured to submit CAM requests to a CAM.

32. A data packet processor as in claim 31, wherein the content of one of the registers is selected from the group consisting of a packet header field, a L2 content addressable memory (CAM) lookup target, a L3 CAM lookup target, and a L4 CAM lookup target.

33. A data packet processor as in claim 28, further comprising a parameter memory accessed by the microprocessor for data packet routing parameters in the parameter memory.

34. A data packet processor as in claim 33, further comprising an aging random access memory (RAM) for monitoring aging of the data packet routing parameters.

35. A data packet processor as in claim 28, further comprising a port tracker which receives the data packets from the input port for pre-processing, prior to providing the data packets to the microprocessor.

36. A data packet processor as in claim 35, wherein the port tracker examines packet contexts of the data packets.

37. A method for processing data packets, comprising:

(a) receiving the data packets from an input port;

(b) processing packet information from the data packets, comprising;

(i) assigning a plurality of registers for storing packet information of the data packets;

(ii) storing the packet information in the registers;

(iii) using a register selection circuit, selecting the content of a selected one of registers as one of a plurality of operands; and

(iv) performing in an arithmetic logic unit an arithmetic or logic operation on the operands to provide a result of the operation; and

(v) feeding back to the register selection circuit the result of the operation to be stored in one of the registers as one of the operands; and

(c) forming CAM lookup targets from the packet information.

38. A method as in claim 37, further comprising:

Performing the CAM lookup using the CAM lookup targets; and

creating a portion of a packet header from the packet information and a result of CAM lookup.

39. A method as in claim 37, further including storing said packet header in a buffer.

40. a method as in claim 37, further comprising:

receiving the contents of the registers into a content-addressable memory (CAM) lookup handler; and

submitting from the CAM lookup handler a CAM request to a CAM, the CAM request being composed based in part on the contents of the registers.

41. A method as in claim 37, wherein the contents of one of the registers is selected from the group consisting of a packet header field, a L2 content addressable memory (CAM) lookup target, a L3 CAM lookup target, and a L4 CAM lookup target.

42. A method as in claim 37, further comprising:

performing a type of service field lookup; and

storing said packet data in a buffer.

43. A method as in claim 37, further including accessing parameters from a parameter memory, said parameters chosen from the group consisting of switching parameters and routing parameters.

44. A method as in claim 43, further comprising monitoring aging of the parameters in an aging random access memory (RAM).

45. A method as in claim 37, further comprising preprocessing the data packets for packet context in a port tracker prior to the step of processing packet information.

46. A method as in claim 45, wherein the preprocessing prepares for each packet a packet status word including information derived from a header of the data packet.

47. A method as in claim 37, wherein the operation is selected from the group consisting of an and operation, an or operation, an xor operation, a neg operation, an add operation, and a compare operation.