Path maintenance mechanism

• US 20080005397A1
• Filed: 07/11/2006
• Published: 01/03/2008
• Est. Priority Date: 05/18/2006
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Aoki, Makoto, Komatsu, Yuki
• Application Number:
  US11/483,669
• Publication Number:
  US 20080005397A1
• Time in Patent Office: Days
• US Class Current: 710/38
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: H04L 45/02 Topology update or discovery

Abstract

In the computer system including a host computer and a storage system, the storage system includes a physical disk and a disk controller, and provides a storage area of the physical disk as at least one logical unit. The processor obtains, at a first time point and a second time point different from the first time point, a relation between a logical path and a component through which the logical path passes, stores, as logical path connection information, the relations obtained at the first time point and the second time point, refers to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other, and specifies the logical path which does not exist at the second time point among the logical paths existing at the first time point.

Claims

1. A computer system, comprising:

at least one host computer including a processor, a memory, and an interface; and

at least one storage system coupled to the host computer,

wherein the storage system comprises a physical disk which stores data requested to be written by the host computer and a disk controller which controls the physical disk, and provides the host computer with a storage area of the physical disk as at least one logical unit,

wherein the processor obtains, at a first time point and a second time point different from the first time point, a relation between a logical path serving as an access route from the host computer to the logical unit and a component through which the logical path passes,

wherein the processor stores, as logical path connection information, the relations obtained at the first time point and the second time point,

wherein the processor refers to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other, and

wherein the processor specifies the logical path which does not exist at the second time point among the logical paths existing at the first time point.

2. The computer system according to claim 1,

wherein the host computer comprises at least one host bus adapter connected to the storage system, the disk controller comprises at least one channel adapter coupled to the host computer, and the component includes the logical unit, the host bus adapter, and the channel adapter, and

wherein, when the logical unit, the host bus adapter, and the channel adapter through which one logical path existing at the first time point passes are respectively identical with the logical unit, the host bus adapter, and the channel adapter through which another logical path existing at the second time point passes, the processor identifies that the one logical path existing at the first time point is identical with the another logical path existing at the second time point.

3. The computer system according to claim 1, wherein the processor further specifies a logical path which does not exist at the first time point among the logical paths existing at the second time point.

4. The computer system according to claim 1, wherein the processor outputs information regarding the specified logical path.

5. The computer system according to claim 1, wherein the processor specifies the logical path existing at both the first time point and the second time point, and outputs information regarding the specified logical path existing at both the first time point and the second time point.

6. The computer system according to claim 1, wherein the processor refers to the logical path connection information to calculate a total number of the logical paths existing at the first time point and a total number of logical paths existing at the second time point, and outputs information regarding the specified logical path, the calculated total number of the logical paths existing at the first time point, and the calculated total number of the logical paths existing at the second time point.

7. The computer system according to claim 1, wherein, when one of the first time point and the second time point is posterior to a last change of a configuration of the computer system, the processor accepts designation of the logical path to be placed online to change a status of the designated logical path to an online status.

8. A logical path difference detecting method for a computer system,

the computer system comprising:

at least one host computer including a processor, a memory, and an interface; and

at least one storage system coupled to the host computer,

the storage system comprising a physical disk which stores data requested to be written by the host computer and a disk controller which controls the physical disk,

the method comprising;

providing, by the storage system, the host computer with a storage area of the physical disk as at least one logical unit;

obtaining, by the host computer, at a first time point and a second time point different from the first time point, a relation between a logical path serving as an access route from the host computer to the logical unit and a component through which the logical path passes;

storing, by the host computer, as logical path connection information, the relations obtained at the first time point and the second time point;

referring, by the host computer, to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other; and

specifying, by the host computer, the logical path which does not exist at the second time point among the logical paths existing at the first time point.

9. The logical path difference detecting method according to claim 8,

wherein the host computer comprises at least one host bus adapter coupled to the storage system, the disk controller comprises at least one channel adapter coupled to the host computer, and the component includes the logical unit, the host bus adapter, and the channel adapter,

the method further comprising identifying, by the host computer, that one logical path existing at the first time point is identical with another logical path existing at the second time point when the logical unit, the host bus adapter, and the channel adapter through which the one logical path existing at the first time point passes are respectively identical with the logical unit, the host bus adapter, and the channel adapter through which the another logical path existing at the second time point passes.

10. The logical path difference detecting method according to claim 8, further comprising specifying, by the host computer, a logical path which does not exist at the first time point among the logical paths existing at the second time point.

11. The logical path difference detecting method according to claim 8, further comprising outputting, by the host computer, information regarding the specified logical path.

12. The logical path difference detecting method according to claim 8, further comprising specifying, by the host computer, the logical path existing at both the first time point and the second time point, and outputting information regarding the specified logical path existing at both the first time point and the second time point.

13. The logical path difference detecting method according to claim 8, further comprising referring, by the host computer, to the logical path connection information to calculate a total number of the logical paths existing at the first time point and a total number of logical paths existing at the second time point, and outputting information regarding the specified logical path, the calculated total number of the logical paths existing at the first time point, and the calculated total number of the logical paths existing at the second time point.

14. A logical path difference detecting method for a computer system,

the computer system comprising:

at least one host computer including a processor, a memory, and an interface;

at least one storage system coupled to the host computer; and

a management computer comprising a processor, a memory, and an interface and being coupled to the host computer,

the storage system comprising a physical disk which stores data requested to be written by the host computer and a disk controller which controls the physical disk,

the method comprising;

providing, by the storage system, the host computer with a storage area of the physical disk for as at least one logical unit;

obtaining, by the management computer, at a first time point and a second time point different from the first time point, a relation between a logical path serving as an access route from the host computer to the logical unit and a component through which the logical path passes;

storing, by the management computer as logical path connection information, the relations obtained at the first time point and the second time point;

referring, by the management computer to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other; and

specifying, by the management computer the logical path which does not exist at the second time point among the logical paths existing at the first time point.

15. The logical path difference detecting method according to claim 14,

wherein the host computer comprises at least one host bus adapter coupled to the storage system, the disk controller comprises at least one channel adapter coupled to the host computer, and the component includes the logical unit, the host bus adapter, and the channel adapter,

the method further comprising identifying, by the management computer that one logical path existing at the first time point is identical with another logical path existing at the second time point when the logical unit, the host bus adapter, and the channel adapter through which the one logical path existing at the first time point passes are respectively identical with the logical unit, the host bus adapter, and the channel adapter through which the another logical path existing at the second time point passes.

16. The logical path difference detecting method according to claim 14, further comprising, by the management computer specifying a logical path which does not exist at the first time point among the logical paths existing at the second time point.

17. The logical path difference detecting method according to claim 14, further comprising outputting, by the management computer information regarding the specified logical path.

18. The logical path difference detecting method according to claim 14, further comprising specifying, by the management computer the logical path existing at both the first time point and the second time point, and outputting information regarding the specified logical path existing at both the first time point and the second time point.

19. The logical path difference detecting method according to claim 14, further comprising referring, by the management computer to the logical path connection information to calculate a total number of the logical paths existing at the first time point and a total number of logical paths existing at the second time point, and outputting information regarding the specified logical path, the calculated total number of the logical paths existing at the first time point, and the calculated total number of the logical paths existing at the second time point.

20. The logical path difference detecting method according to claim 14, further comprising accepting, by the management computer designation of the logical path to be placed online when one of the first time point and the second time point is posterior to a last change of a configuration of the computer system, and instructing the host computer to change a status of the designated logical path to an online status.