TRANSFORMER COILS FOR PROVIDING VOLTAGE ISOLATION

• US 20080013635A1
• Filed: 06/28/2007
• Published: 01/17/2008
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: DUPUIS, TIMOTHY
• Granted Patent: US 7,856,219 B2
• Time in Patent Office: Days
• US Class Current: 375/258
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1204 : Optical Diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/33523 : with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H04L 25/0266 : Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A circuit package providing voltage isolation includes at least one output and first circuitry located in a substrate of the circuit package for performing an operation. A transformer located in the metal layers of the circuit package provides voltage isolation between the first circuitry and the at least one output.

Claims

1. An integrated isolator system, comprising:

a first integrated circuit chip containing functional circuitry;

a second integrated circuit chip containing functional circuitry;

a first transformer within the first integrated circuit chip for providing voltage isolation for the first integrated circuit chip;

a second transformer within the second integrated circuit chip for providing voltage isolation for the second integrated circuit chip; and

wherein the first transformer is interconnected with the second transformer via bond wires to provide voltage isolation between the first chip and the second chip.

2. The integrated isolator system of claim 1, wherein the first transformer and the second transformer each further comprise:

a primary coil located in a first metal layer of the first integrated circuit chip and the second integrated circuit chip; and

a secondary coil located in a second metal layer of the first integrated circuit chip and the second integrated circuit chip.

3. The integrated isolator system of claim 2, wherein the primary coil and the secondary coil are substantially non-overlapping.

4. The integrated isolator system of claim 2, wherein the primary coil and the secondary coil are separated by a high voltage dielectric to increase a breakdown voltage of the first transformer and the second transformer.

5. The integrated isolator system of claim 2, wherein the primary coil and the secondary coil are diagonally offset from each other to increase a breakdown voltage of the first transformer and the second transformer.

6. The integrated isolator system of claim 2, wherein the primary coil is located in the Metal 2 layer and the secondary coil is located in the Metal 5 layer of the first and second integrated circuit chips.

7. The integrated isolator system of claim 6 further including:

first and second terminals connected with each of the primary coils and located in the Metal 1 layer; and

first and second bonding pads connected with each of the secondary coils and located in the Metal 5 layer.

8. The integrated isolator system of claim 6 further including a center-tap with the primary coils, comprising:

a conductive strip located in the Metal 1 layer; and

a conductive via connecting the conductive strip in the Metal layer 1 with the primary coil in Metal 2 layer.

9. The integrated isolator system of claim 2, wherein the first transformer comprises a plurality of first transformers and the second transformer comprises a plurality of second transformers, each of the plurality of first transformers connected to an associated second transformer and defining a communications channel therebetween.

10. The integrated isolator system of claim 9, wherein the plurality of first transformers define output communications channels in a first orientation and the plurality of second transformers define output communications channel in a second orientation that is a reverse of the first orientation.

11. The integrated isolator system of claim 1, wherein the first integrated circuit chip and the second integrated circuit chip comprise CMOS devices.

12. An integrated isolator system, comprising:

a first integrated circuit chip containing functional CMOS circuitry;

a second integrated circuit chip containing functional CMOS circuitry;

a first transformer associated with the first integrated circuit chip for providing voltage isolation for the first integrated circuit chip, comprising;

a first primary coil located in a first metal layer of the first integrated circuit chip;

a first secondary coil located in a second metal layer of the first integrated circuit chip;

wherein the first primary coils and the first secondary coils are substantially non-overlapping;

a second transformer associated with the second integrated circuit chip for providing voltage isolation for the second integrated circuit chip;

a second primary coil located in a first metal layer of the second integrated circuit chip; and

a second secondary coil located in a second metal layer of the second integrated circuit chip;

wherein the second primary coils and the second secondary coils are substantially non-overlapping;

wherein the first transformer is interconnected with the second transformer via bond wires to provide voltage isolation between the first chip and the second integrated circuit chip.

13. The integrated isolator system of claim 12, wherein the first and second primary coils and the first and second secondary coils are separated by a high voltage dielectric to increase a breakdown voltage of the first transformer and the second transformer.

14. The integrated isolator system of claim 12, wherein the first and second primary coils and the first and second secondary coils are diagonally offset from each other to increase a breakdown voltage of the first transformer and the second transformer.

15. The integrated isolator system of claim 12, wherein the first and second primary coils are located in the Metal 2 layer of the first and second chips and the first and second secondary coils are located in the Metal 5 layer of the first and second integrated circuit chips.

16. The integrated isolator system of claim 15 further including:

first and second terminals associated with each of the first and second primary coils and located in the Metal 1 layer; and

first and second bonding pads associated with each of the first and second secondary coils and located in the Metal 5 layer.

17. The integrated isolator system of claim 15 further including a center-tap with the first and second primary coils, comprising:

a conductive strip located in the Metal 1 layer; and

a conductive via connecting the conductive strip in the Metal layer 1 with the primary coil in Metal layer 2.

18. The integrated isolator system of claim 12, wherein the first transformer comprises a plurality of first transformers and the second transformer comprises a plurality of second transformers, each of the plurality of first transformers connected to an associated second transformer and defining a communications channel therebetween.

19. The integrated isolator system of claim 18, wherein the plurality of first transformers define output communications channels in a first orientation and the plurality of second transformers define output communications channel in a second orientation that is a reverse of the first orientation.

20. An integrated isolator, comprising:

first and second integrated circuit substrates;

each of said first and second substrates having contained on the surface thereof a lower transformer coil with an associated input;

each said lower transformer coil on said first and second substrates having a layer of dielectric material disposed thereover; and

a top conductive coupling layer disposed over each of said respective dielectric layers on said first and second substrates to couple energy from one of said inputs of said respective lower transformer coils on said first and second substrates to the other of said inputs.

21. The isolator of claim 20, wherein said top conductive coupling layer and each of said respective lower transformer coils on said first and second substrates are fabricated as an integral part of said first and second substrates.

22. The isolator of claim 20, wherein said top conductive coupling layer comprises:

a respective upper transformer coil for each of said first and second substrates disposed over said respective lower transformer coil and separated therefrom by said associated dielectric layer, each of said upper transformer coils having an input; and

said inputs of each of said upper transformer coils on said first and second substrates, respectively, conductively connected together with a conductive medium.

23. The isolator of claim 22, wherein said conductive medium comprises bond wires.

24. The isolator of claim 22, wherein said upper and lower transformer coils are planar.

25. The isolator of claim 22, wherein said first and second substrates are fabricated with a CMOS process and said upper and lower transformers are fabricated in metal layers that are part of said CMOS process.

26. The isolator of claim 20, wherein said first and second substrates are mounted in an integrated circuit package.

27. The isolator of claim 26, wherein one of said first and second substrates has an interface associated therewith for interfacing between an interface pin on said integrated circuit package and the input of said associated lower transformer coil.

28. The isolator of claim 27, wherein said interface comprises a driver circuit for driving the input of said associated lower transformer coil with a signal.

29. The isolator of claim 27, wherein said interface comprises a receiver circuit for receiving from the input of said associated lower transformer coil a signal.

30. The isolator of claim 20, wherein each of said first and second substrates has an interface associated therewith for interfacing between a respective first or second interface pin on said integrated circuit package and the input of said associated lower transformer coil.

31. The isolator of claim 30, wherein said interface on one of said first and second substrates comprises a driver for driving the input of said associated lower transformer coil with a signal.

32. The isolator of claim 30, wherein said interface on one of said first and second substrates comprises a receiver for receiving a signal from the input of said associated lower transformer.

33. The isolator of claim 30, wherein said interface on one of said first and second substrates comprises a driver for driving the input of said associated lower transformer coil with a signal and said interface on the of said first and second substrates comprises a receiver for receiving a signal from the input of said associated lower transformer coil.

34. The isolator of claim 27, wherein said first and second substrates are isolated from each other.