Inspection System, Inspection Method, and Method for Manufacturing Semiconductor Device

• US 20080024156A1
• Filed: 09/27/2007
• Published: 01/31/2008
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki, Akiba, Mai, Tachimura, Yuko
• Granted Patent: US 7,463,049 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G06K 7/0095 Testing the sensing arrangement, e.g. testing if a magnetic card reader, bar code reader, RFID interrogator or smart card reader functions properly testing of electrical circuits G01R31/28

Abstract

The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit.

Claims

1-12. -12. (canceled)

13. An inspection method comprising:

supplying a signal or power supply voltage to each of a plurality of chips without contact using an antenna of each of the plurality of chips;

moving an inspection electrode with an arbitrary portion of the antenna or the whole antenna of each of the plurality of chips overlapped with the inspection electrode with a space therebetween; and

grasping an operating state of each of the plurality of chips from a voltage of the inspection electrode and a position of the inspection electrode.

15. The inspection method according to claim 13, wherein the chip includes a substrate, and an antenna and an integrated circuit over the substrate, and the substrate is an insulator.

17. The inspection method according to claim 15, wherein the substrate is a glass substrate or a plastic substrate.

19. The inspection method according to claim 13, wherein the space between each antenna of the plurality of chips and the plurality of the inspection electrodes is controlled by flowing a fluid thereinto.

21. The inspection method according to claim 13, wherein voltage applied to each antenna of the plurality of chips is calculated by a method of successive approximation, a Fourier transform method using a projection slice theorem, or a convolution theorem method to grasp an operating state of each of the plurality of chips.

23. The inspection method according to claim 13, wherein the inspection electrode is rotated.

14. An inspection method comprising:

overlapping each antenna of a plurality of chips with an inspection electrode with a space therebetween to supply a signal or power supply voltage to each of the plurality of chips without contact;

moving the inspection electrode with an arbitrary portion of the antenna or the whole antenna of each the plurality of chips overlapped with the inspection electrode with a space therebetween; and

grasping an operating state of each of the plurality of chips from a voltage of the inspection electrode and a position of the inspection electrode to the plurality of chips.

16. The inspection method according to claim 14, wherein the chip includes a substrate, and an antenna and an integrated circuit over the substrate, and the substrate is an insulator.

18. The inspection method according to claim 16, wherein the substrate is a glass substrate or a plastic substrate.

20. The inspection method according to claim 14, wherein the space between each antenna of the plurality of chips and the plurality of the inspection electrodes is controlled by flowing a fluid thereinto.

22. The inspection method according to claim 14, wherein voltage applied to each antenna of the plurality of chips is calculated by a method of successive approximation, a Fourier transform method using a projection slice theorem, or a convolution theorem method to grasp an operating state of each of the plurality of chips.

24. The inspection method according to claim 14, wherein the inspection electrode is rotated.

25-40. -40. (canceled)