Method for fabricating an integrated gate dielectric layer for field effect transistors

• US 20080026553A1
• Filed: 07/31/2006
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Swenberg, Johanes, Chua, Thai Cheng, Kher, Shreyas, Wang, Chikuang Charles, Muthukrisnan, Shankar, Uritsky, Yuri, Conti, Giuseppina
• Granted Patent: US 7,601,648 B2
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/02046 Dry cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/02052 Wet cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02315 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane

Abstract

Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.

Claims

1. A method for forming gate dielectric layers on a substrate, comprising:

forming a silicon oxide layer on a substrate;

plasma treating the silicon oxide layer;

depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and

thermal annealing the substrate.

2. The method of claim 1, wherein the step of plasma treating the silicon oxide layer further comprises:

flowing an inert gas into a plasma treatment chamber; and

forming a plasma by the inert gas.

3. The method of claim 2, wherein the step of flowing the inert gas further comprises:

flowing the inert gas between about 50 sccm and about 750 sccm into the plasma treatment chamber.

4. The method of claim 2, wherein the step of forming a plasma further comprises:

applying a RF power between about 500 Watts and about 3000 Watts.

5. The method of claim 2, wherein the inert gas is selected from a group consisting of Ar, He, Ne, Xe, and the combination thereof.

6. The method of claim 2, wherein the inert gas is a nitrogen containing gas.

7. The method of claim 6, wherein the treated silicon oxide layer treated by the nitrogen containing gas has a nitrogen concentration between about 0.2 E¹⁵ atoms/cm₂ to about 1 E¹⁵ atoms/cm₂.

8. The method of claim 1, further comprising:

precleaning the substrate prior to forming the silicon oxide layer.

9. The method of claim 1, wherein the step of forming the silicon oxide layer, further comprises:

forming the silicon oxide layer with a thickness less than 15 Å

.

10. The method of claim 1, wherein depositing the silicon nitride layer further comprises:

depositing the silicon nitride with a thickness less than 15 Å

.

11. The method of claim 1, wherein the step of depositing the silicon nitride layer further comprises:

alternatively flowing a silicon containing gas and a nitrogen containing gas into an ALD chamber.

12. The method of claim 11, wherein the step of flowing further comprises:

flowing the silicon containing gas into the ALD chamber between about 5 sccm and about 500 sccm; and

flowing the nitrogen containing gas into the ALD chamber between about 1000 sccm and about 5000 sccm.

13. The method of claim 11, wherein the nitrogen containing gas is at least one of NH₃, N₂, N₂H₄ or N₂O.

14. The method of claim 11, wherein the silicon containing gas is at least one of SiH₄, Si₂H₆, dichlorosilane (DCS), tetrachlorosilane (TCS) or hexachlorodisilane (HCD).

15. The method of claim 1, wherein the silicon oxide layer and the silicon nitride layer form a gate dielectric layer.

16. The method of claim 1, wherein the step of plasma treating the silicon oxide layer further comprises:

creating nucleation sites on the treated silicon oxide layer.

17. A method for forming gate dielectric layers on a substrate, comprising:

precleaning a substrate;

forming a silicon oxide layer on the substrate;

plasma treating the silicon oxide layer;

depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and

thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer form a gate dielectric layer.

18. The method of claim 17, wherein the plasma treating the silicon oxide layer further comprises:

creating nucleation sites on the treated silicon oxide layer.

19. The method of claim 17, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å

.

20. A method for forming a gate structure, comprising:

precleaning a substrate;

forming a silicon oxide layer on the substrate;

plasma treating the silicon oxide layer;

depositing a silicon nitride layer on the silicon oxide layer by an ALD process;

thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å and

forms a gate dielectric;

forming a gate electrode on the gate dielectric; and

forming source and drain regions in the substrate proximate the gate electrode.