Electronic device including a conductive stud over a bonding pad region and a process for forming the electronic device

• US 20080029887A1
• Filed: 08/07/2006
• Published: 02/07/2008
• Est. Priority Date: 08/07/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: T. Lee, Tien Yu, Tang, Jinbang, Ramanathan, Lakshmi N.
• Granted Patent: US 7,812,448 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein from a top view, the conductive stud (34) lies substantially completely within the opening (112, 24). The process can also include forming a second barrier layer (52) overlying the conductive stud (34).

Claims

1. An electronic device comprising:

an interconnect level including a bonding pad region;

an insulating layer overlying the interconnect level and including a first opening over the bonding pad region;

a barrier layer lying along a side and a bottom of the first opening, wherein the barrier layer includes;

a first surface adjacent to the first opening; and

a second surface opposite the first surface and defining a second opening; and

a conductive stud lying within the second opening, wherein the conductive stud substantially fills the second opening, and a majority of the conductive stud lies within the second opening.

2. The electronic device of claim 1, wherein substantially all of the conductive stud lies within the second opening.

3. The electronic device of claim 1, wherein the insulating layer comprises a nitride layer, an oxynitride layer, or any combination thereof.

4. The electronic device of claim 1, wherein the conductive stud comprises Ag, Au, Cu, Pt, or any combination thereof.

5. The electronic device of claim 1, wherein the conductive stud has a height of greater than approximately 1 micron.

6. An electronic device comprising:

an interconnect level including a bonding pad region;

an insulating layer overlying the interconnect level and including an opening over the bonding pad region; and

a conductive stud lying within the opening over the bonding pad region, wherein the conductive stud is substantially encapsulated, and a majority of the conductive stud comprises Cu, Ag, Au, Pt, or any combination thereof.

7. The electronic device of claim 6, further comprising a first barrier layer lying between the conductive stud and the bonding pad region of the interconnect layer.

8. The electronic device of claim 7, further comprising a second barrier layer overlying and immediately adjacent to the conductive stud.

9. The electronic device of claim 6, wherein an under-bump metallization layer comprises the second barrier layer.

10. The electronic device of claim 6, wherein the insulating layer includes a nitride, an oxynitride, or any combination thereof.

11. The electronic device of claim 6, wherein the insulating layer is greater than approximately 1 micron in thickness.

12. The electronic device of claim 6, wherein from a top view, the conductive stud lies substantially completely within the opening in the insulating layer.

13. A process for forming an electronic device comprising:

forming an interconnect level over a substrate, wherein the interconnect level further includes a bonding pad region;

forming an insulating layer overlying the interconnect level;

forming an opening in the insulating layer to expose the bonding pad region;

forming a first barrier layer within the opening;

forming a conductive stud within the opening, wherein from a top view, the conductive stud lies substantially completely within the opening; and

forming a second barrier layer overlying the conductive stud.

14. The process of claim 13, wherein forming the insulating layer includes forming a nitride layer.

15. The process of claim 13, further comprising forming a seed layer after forming the first barrier layer.

16. The process of claim 15, wherein forming the conductive stud comprises plating a conductive layer.

17. The process of claim 16, wherein forming the conductive stud comprises:

forming a sacrificial layer including an opening over the bonding pad region prior to plating the a conductive layer;

removing the sacrificial layer after plating the conductive layer; and

removing exposed portions of the first barrier layer and the seed layer after plating the conductive layer.

18. The process of claim 17, wherein removing the exposed portions of the first barrier layer includes using a chemical mechanical polishing process.

19. The process of claim 13, further comprising forming a passivation layer including an opening over the bonding pad region, after forming the conductive stud, and prior to forming the second barrier layer.

20. The process of claim 13, wherein the second barrier layer is a part of an under-bump metallization layer immediately adjacent to the conductive stud.