PATTERN INSPECTION METHOD AND ITS APPARATUS

• US 20080031511A1
• Filed: 10/09/2007
• Published: 02/07/2008
• Est. Priority Date: 01/30/2002
• Status: Active Grant

• Current Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.), Hitachi, Ltd.
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Goto, Hiroshi, Sakai, Kaoru, Okabe, Takafumi, Maeda, Shunji, Takeuchi, Naoya, Kuwabara, Masayuki
• Granted Patent: US 7,711,178 B2
• Time in Patent Office: Days
• US Class Current: 382/149
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0002 Inspection of images, e.g. flaw detection
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/32 using correlation-based methods
• CPC Class Codes: G06T 7/33 using feature-based methods

Abstract

A pattern inspection method including: sequentially imaging plural chips formed on a substrate; selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip and reference image stored in memory from an image of a firstly imaged chip among said sequentially imaged plural chips formed on the substrate; computing position gap between an inspection image of a chip obtained by the sequential imaging and reference image stored in a memory by using a positional information of a pattern image included in the inspection image and a reference pattern image included in the reference image which are both corresponding to the pattern selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image and extracting a difference as a defect candidate.

Claims

1. A pattern inspection method comprising:

sequentially imaging plural chips formed on a substrate;

selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip and a reference image stored in a memory from an image of a firstly imaged chip among said sequentially imaged plural chips formed on the substrate;

computing position gap between an inspection image of a chip obtained by the sequential imaging and reference image stored in a memory by using a positional information of a pattern image included in the inspection image and a reference pattern image included in the reference image which are both corresponding to the pattern selected at the selecting;

aligning the inspection image and the reference image by using information of the calculated position gap; and

comparing the aligned inspection image with the reference image and extracting a difference between the two images as a defect candidate.

2. A pattern inspection method according to claim 1, wherein in the selecting, the pattern is selected from plural patterns formed in the firstly imaged chip using edge information of each pattern included in the firstly imaged chip.

3. A pattern inspection method according to claim 1, wherein in the selecting, the pattern is selected from a region where plural patterns are formed in the firstly imaged chip.

4. A pattern inspection method according to claim 3, wherein in the selecting, the pattern is selected from plural patterns formed in the firstly imaged chip using edge information of each pattern included in the firstly imaged chip.

5. A pattern inspection method according to the claim 1, wherein in the selecting, the pattern is selected from an image of a firstly detected chip before acquisition of an image of a secondary detected chip is completed in the sequentially imaging.

6. A pattern inspection apparatus comprising:

image acquisition unit which sequentially detects images of a manufactured product on which plural chips are formed;

pattern selecting unit for selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip detected by the image acquisition unit and a reference image stored in a memory from an image of a firstly detected chip detected by the image acquisition unit among the sequentially detected plural chips formed on the substrate;

computing unit for computing position gap between an inspection image of a chip formed on the substrate and a reference image stored in a memory by comparing an image of a pattern included in each images which are corresponding to the pattern selected by the pattern selecting unit;

aligning unit for aligning the inspection image and the reference image by using information of the calculated position gap; and

defect candidate extracting unit which compares the aligned inspection image with the reference image, and extracting a difference between the inspection image and the reference as a defect candidate.

7. A pattern inspection apparatus according to claim 6, wherein the pattern selecting unit selects the pattern among plural patterns formed in the firstly detected chip using edge information of each pattern included in the firstly imaged chip.

8. A pattern inspection apparatus according to claim 6, wherein the pattern selecting unit selects the pattern from a region where plural patterns are formed in the firstly imaged chip.

9. A pattern inspection apparatus according to the claim 8, wherein the pattern selecting unit selects the pattern among plural patterns formed in the firstly imaged chip using edge information of each pattern included in the firstly imaged chip.

10. A pattern inspection apparatus according to the claim 6, wherein the pattern selecting unit selecting a pattern which is suitable for calculating position gap from an image of a firstly detected chip before acquisition of an image of a secondary detected chip is completed by the image acquisition unit.