Semiconductor Device With Damage Detection Circuit and Method for Producing the Same

• US 20080035923A1
• Filed: 08/10/2007
• Published: 02/14/2008
• Est. Priority Date: 08/10/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Holl, Guenter, Zojer, Gerhard, Tschmelitsch, Andreas, Herzele, Guenter
• Granted Patent: US 8,575,723 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.

Claims

1. A semiconductor chip, comprising:

a current source coupled between a first potential and an electrical node;

a detection circuit having an input coupled to the electrical node; and

a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.

2. The semiconductor chip of claim 1, further comprising:

a second active component coupled in series with the current source and further coupled between the first active component and the second potential, wherein the second active component is coupled to the first active component via a second conductive interconnect.

3. The semiconductor chip of claim 2, wherein the first and second active components are each a transistor.

4. The semiconductor chip of claim 2, wherein the first and second active components are each a diode.

5. The semiconductor chip of claim 2, wherein the semiconductor chip has a central zone and a plurality of edges surrounding the central zone, and the first and second conductive interconnects each runs in a direction parallel with a different one of the edges.

6. The semiconductor chip of claim 2, further comprising:

a third active component coupled in series with the current source and further coupled between the second active component and the second potential, wherein the third active component is coupled to the first active component via a third conductive interconnect; and

a fourth active component coupled in series with the current source and further coupled between the third active component and the second potential, wherein the fourth active component is coupled to the first active component via a fourth conductive interconnect.

7. The semiconductor chip of claim 6, wherein the semiconductor chip has a central zone and a plurality of edges surrounding the central zone, and the first, second, third, and fourth conductive interconnects each runs in a direction parallel with a different one of the edges.

8. The semiconductor chip of claim 1, further comprising:

a dielectric layer; and

a crack stop formed as a ring in the dielectric layer, the ring having four sides enclosing a central zone,

wherein the first conductive interconnect runs, in parallel with one of the sides of the ring, between the central zone and the crack stop.

9. The semiconductor chip of claim 8, wherein a distance between the crack stop the first conductive interconnect is less than or equal to 2 μ

m.

10. The semiconductor chip of claim 1, wherein the current source is configured to generate a current in a range of 1 μ

A to 20 μ

A, inclusive.

11. The semiconductor chip of claim 1, wherein the first active component is part of a temperature sensor.

12. The semiconductor chip of claim 11, wherein the semiconductor chip has a plurality of lateral edges and a plurality of corners produced by points of intersection of the lateral edges, and the temperature sensor is configured to determine a temperature based on a combination of temperatures at each of the corners.

13. The semiconductor chip of claim 1, wherein the detection circuit comprises a differential amplifier, wherein the input of the detection circuit is an input of the differential amplifier.

14. A semiconductor chip having a plurality of lateral edges, the semiconductor chip comprising:

a current source having a current output;

a differential amplifier having an input coupled to the current output;

a plurality of circuit elements coupled in series with each other between the current output and a fixed potential, each of the circuit elements configured to function as a diode; and

a plurality of conductive interconnects coupled between the plurality of transistors and each running in parallel with a different one of the lateral edges.

15. The semiconductor chip of claim 14, wherein each of the plurality of circuit elements is a transistor having a gate and a collector connected together.

16. The semiconductor chip of claim 14, wherein each of the plurality of circuit elements is a diode.

17. The semiconductor chip of claim 14, further comprising:

a semiconductor layer in which the plurality of circuit elements are disposed;

a dielectric layer disposed over the semiconductor layer, the plurality of conductive interconnects being disposed in the dielectric layer; and

a crack stop disposed in the dielectric layer.

18. The semiconductor chip of claim 17, wherein the crack stop is formed as a ring having a plurality of sides each in parallel with a different one of the lateral edges of the semiconductor chip.

19. The semiconductor chip of claim 18, wherein the ring of the crack stop surrounds the plurality of conductive interconnects.

20. The semiconductor chip of claim 14, wherein the plurality of lateral edges intersect to form a plurality of corners of the semiconductor chip, each of the plurality of circuit elements being disposed at a different one of the corners.