PARALLEL DATA PROCESSING APPARATUS
First Claim
1. A data processing apparatus comprising:
- a SIMD (single instruction multiple data) array of processing elements, each of which includes an internal memory unit, the processing elements being divided into a plurality of processing blocks, which processing blocks are operable to process respective groups of data items;
an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another; and
a data transfer controller operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.
3 Assignments
0 Petitions
Accused Products
Abstract
A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.
-
Citations
49 Claims
-
1. A data processing apparatus comprising:
-
a SIMD (single instruction multiple data) array of processing elements, each of which includes an internal memory unit, the processing elements being divided into a plurality of processing blocks, which processing blocks are operable to process respective groups of data items;
an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another; and
a data transfer controller operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
-
-
26. A data processing apparatus comprising:
-
a SIMD (single instruction multiple data) array of processing elements, each of which includes an internal memory unit;
an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another; and
a data transfer controller operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
-
Specification