Method, apparatus and system providing a storage gate pixel with high dynamic range

• US 20080055441A1
• Filed: 08/29/2006
• Published: 03/06/2008
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Altice, Parker
• Granted Patent: US 8,026,966 B2
• Time in Patent Office: Days
• US Class Current: 348/297
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/622 by controlling anti-blooming drains
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.

Claims

1. A method of operating a pixel, the method comprising:

accumulating a first amount of charge in a photosensor for a first period of time;

transferring the first amount of charge to a storage node;

accumulating a second amount of charge in the photosensor for a second period of time;

transferring the second amount of charge to the storage node, said storage node accumulating said first and second amounts of charge; and

,

transferring the first and second accumulated amounts of charge from the storage node to a floating diffusion node.

2. The method of claim 1 further comprising reading out the charge residing in the floating diffusion node as a pixel output signal.

3. The method of claim 1 further comprising pulsing a signal at a gate of an anti-blooming transistor coupled to the photosensor to reset the photosensor.

4. The method of claim 1 further comprising maintaining a constant voltage at a gate of an anti-blooming transistor coupled to the photosensor during the acts of accumulating and transferring.

5. The method of claim 1 wherein the first and second periods of time are equal.

6. The method of claim 1 wherein the first and second periods of time are not equal.

7. The method of claim 4 further comprising controlling the charge transfer from the photosensor to the storage node with a transistor.

8. The method of claim 4 further comprising diverting excess charge from the photosensor with said anti-blooming transistor.

9. The method of claim 4 further comprising accumulating a third amount of charge in the photosensor for a third amount of time and transferring the third amount of charge to the storage node prior to transferring the first and second amounts of charge from the storage node, said storage node accumulating said first, second and third amounts of charge.

10. The method of claim 9 further comprising transferring the accumulated charge at the storage node to the floating diffusion node.

11. The method of claim 9 wherein the first, second and third periods of time are equal.

12. The method of claim 9 wherein the first, second and third periods of time are not equal.

13. The method of claim 9 wherein the first, second and third periods of time successively decrease.

14. The method of claim 9 wherein the first, second and third periods of time successively increase.

15. The method of claim 9 further comprising subtracting a value related to fixed pattern noise from the output signal.

16. A method of operating an imager circuit having at least one pixel circuit, said method comprising:

resetting the charge stored in a photosensor to a known state;

accumulating a first amount of charge in a photosensor for a first period of time;

transferring the first amount of charge to a storage node;

accumulating a second amount of charge in the photosensor for a second period of time;

transferring the second amount of charge to the storage node, said storage node accumulating said first and second amounts of charge;

transferring the first and second accumulated amounts of charge from the storage node to a floating diffusion node; and

reading out the charge residing in the floating diffusion node as a pixel output signal.

17. The method of claim 16, where the reset is executed by pulsing a signal on an anti-blooming transistor gate.

18. The method of claim 16, further comprising subtracting a value representing fixed pattern noise from the output signal.

19. The method of claim 18 wherein the value related to fixed pattern noise is determined using a look-up table.

20. An imager circuit comprising:

at least one pixel circuit, said at least one pixel circuit comprising;

a photosensor having a charge storage capacity, the photosensor configured to accumulate charge;

a first transistor connected to the photosensor for transferring charge from the photosensor;

a storage node selectively coupled to the photosensor for receiving charge from the photosensor via the first transistor;

a second transistor connected to the storage node for transferring charge from the storage node to a floating diffusion node; and

a control circuit for operating said first transistor to define a plurality of successive integration periods during an image capture in which charges produced by said photosensor in each integration period are successively stored and accumulated in said storage node, said control circuit being configured to operate said second transistor to transfer charges accumulated in said storage node for said integration periods to said floating diffusion region.

21. The circuit of claim 20 where the storage node has a storage capacity of at least about twice the storage capacity of the photosensor

22. The circuit of claim 20 further comprising a readout circuit connected to the floating diffusion node to output a signal based on the charge stored at the floating diffusion node.

23. The circuit of claim 22 wherein the readout circuit further comprises:

a reset transistor connected to the floating diffusion node for resetting the charge on the floating diffusion node;

a source-follower transistor having a gate for receiving charge from the floating diffusion node; and

a row-select transistor connected to the source-follower transistor for outputting a signal produced by the source-follower transistor.

24. The circuit of claim 23 further comprising an anti-blooming transistor electrically connected to the photosensor for draining charge from the photosensor.

25. The circuit of claim 23, wherein said control circuit is operable to apply a constant voltage to a gate of said anti-blooming transistor during said plurality of successive integration periods.

26. An imaging device comprising:

a pixel array comprising a plurality of pixels, wherein at least some of said pixels comprise;

a photosensor having a charge storage capacity, the photosensor configured to accumulate charge;

a first transistor connected to the photosensor for transferring charge from the photosensor;

a storage node coupled to the photosensor for receiving charge from the photosensor via the first transistor;

a second transistor connected to the storage node for transferring charge from the storage node to a floating diffusion node; and

a control circuit for operating said first transistor to define a plurality of successive integration periods during an image capture in which charges produced by said photosensor in each integration period are successively stored and accumulated in said storage node, said control circuit being configured to operate said second transistor to transfer charges accumulated in said storage node for said integration periods to said floating diffusion region.

27. The imaging device of claim 26 where the storage node charge storage capacity is at least about twice the storage capacity of the photosensor.

28. The imaging device of claim 26, wherein said pixels further comprise a readout circuit connected to the floating diffusion node to output a signal based on the charge accumulated at the floating diffusion region.

29. An processing system comprising:

a processor; and

an imaging device coupled to said processor, said imaging device comprising an array of pixels, each of said pixels comprising;

a photo-conversion device for generating charges;

a first transistor connected to the photosensor for transferring charge from the photosensor;

a storage node selectively coupled to the photosensor for receiving charge from the photosensor via the first transistor;

a second transistor connected to the storage node for transferring charge from the storage node to a floating diffusion node; and

a control circuit for operating said first transistor to define a plurality of successive integration periods during an image capture in which charges produced by said photosensor in each integration period are successively stored and accumulated in said storage node, said control circuit being configured to operate said second transistor to transfer charges accumulated in said storage node for said integration periods to said floating diffusion region

30. The system of claim 29 wherein the storage node charge storage capacity is at least-about twice the storage capacity of the photosensor.

31. The system of claim 29 wherein the pixel further comprises a readout circuit connected to the floating diffusion node to output a signal based on the charge accumulated at the floating diffusion gate.

32. The system of claim 30 wherein the readout circuit further comprises:

a reset transistor connected to the floating diffusion node for resetting the charge on the floating diffusion node;

a source-follower transistor having a gate for receiving charge from the floating diffusion node; and

a row-select transistor connected to the source-follower transistor for outputting a signal produced by the source-follower transistor.

33. The system of claim 32 further comprising an anti-blooming transistor electrically connected to the photosensor for draining charge from the photosensor.

34. The circuit of claim 32, wherein said control circuit is operable to apply a constant voltage to a gate of said anti-blooming transistor during said plurality of successive integration periods.

35. The system of claim 32 wherein said system is a camera processor system.