MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES

• US 20080059769A1
• Filed: 08/30/2006
• Published: 03/06/2008
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Rymarczyk, James Walter, Ignatowski, Michael, Heller, Thomas J.
• Granted Patent: US 8,028,290 B2
• Time in Patent Office: Days
• US Class Current: 712/209
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Claims

1. A processor for executing program instructions, wherein said program instructions comprise program instructions belonging to a first instruction set architecture and a second instruction set architecture distinct from said first instruction set architecture, said processor comprising:

a plurality of execution cores integrated on at least one die, wherein at least a first one of said multiple cores is capable of executing program instructions of said first instruction set architecture, and wherein at least a second one of said multiple cores is capable of executing program instructions of said second instruction set architecture; and

a package for containing said plurality of execution cores and providing electrical terminals for interfacing said processor to external devices.

2. The processor of claim 1, wherein said plurality of execution cores is integrated on a single die within said package.

3. The processor of claim 1, wherein said first core is capable of executing only instructions of said first instruction set architecture and wherein said second core is capable of executing instructions only of said second instruction set architecture.

4. The processor of claim 1, further comprising:

a first level cache coupled to each of said multiple cores; and

a power management unit for selecting only a given one of said multiple cores for operation in response to a selection value specifying said given core.

5. The processor of claim 1, further comprising a plurality of a first level caches in a number equal to a quantity of said multiple cores, wherein each of said first level caches is associated with an associated one of said first level caches, whereby multiple ones of said multiple cores can be simultaneously operated.

6. The processor of claim 5, further comprising a power management unit for selecting one or more of said multiple cores for operation in response to one or more selection values specifying said one or more cores.

7. The processor of claim 5, wherein said power management unit further manages power to said first level caches, and wherein said power management unit disables power to said first level caches that are associated with disabled ones of said multiple cores.

8. The processor of claim 1, wherein said first instruction set architecture is a power PC architecture.

9. The processor of claim 1, wherein said first instruction set architecture is an iX6 architecture.

10. The processor of claim 1, wherein said first instruction set architecture is a system Z architecture.

11. A method of managing operation of a processing system supporting multiple instruction set architectures, wherein said processing system supports execution of multiple operating system images within multiple virtual machines, said method comprising:

receiving a request to instantiate a virtual machine having a specified instruction set architecture;

determining an availability status of given core within a processor having multiple cores, at least one supporting said specified instruction set architecture and at least one other not supporting said specified instruction set architecture; and

in response to determining that said given core is available, instantiating said virtual machine on said core.

12. The method of claim 11, further comprising in response to determining that said given core is not available, failing instantiation of said virtual machine.

13. The method of claim 11, further comprising:

determining whether or not said given core is disabled; and

enabling said given core in response to determining that said given core is disabled.

14. A processing system comprising:

a memory for storing program instructions and data; and

a processor for executing said program instructions, said program instructions including multiple operating systems executing within multiple virtual machines, wherein said program instructions further comprise hypervisor program instructions for managing said virtual machines, and wherein said hypervisor program instructions comprise program instructions for

receiving a request to instantiate a virtual machine having a specified instruction set architecture,

determining an availability status of given core within a processor having multiple cores, at least one supporting said specified instruction set architecture and at least one other not supporting said specified instruction set architecture, and

instantiating said virtual machine on said core in response to determining that said given core is available.

15. The processing system of claim 14, wherein said program instructions further comprise program instructions for failing instantiation of said virtual machine in response to determining that said given core is not available.

16. The processing system of claim 14, further comprising program instructions for:

determining whether or not said given core is disabled; and

enabling said given core in response to determining that said given core is disabled.

17. The processing system of claim 16, wherein said program instructions for enabling enable only one of said multiple cores and disable any other active cores in response to determining that said given core is disabled.

18. A computer program product comprising computer-readable storage media encoding program instructions for execution within a processing system supporting execution of multiple operating system images executing within multiple virtual machines, wherein said program instructions comprise hypervisor program instructions for managing said virtual machines, and wherein said hypervisor program instructions comprise program instructions for

receiving a request to instantiate a virtual machine having a specified instruction set architecture,

determining an availability status of given core within a processor having multiple cores, at least one supporting said specified instruction set architecture and at least one other not supporting said specified instruction set architecture, and

instantiating said virtual machine on said core in response to determining that said given core is available.

19. The computer program product of claim 18, wherein said program instructions further comprise program instructions for failing instantiation of said virtual machine in response to determining that said given core is not available.

20. The computer program product of claim 18, further comprising program instructions for:

determining whether or not said given core is disabled; and

enabling said given core in response to determining that said given core is disabled.