Method of Actively Tagging Electronic Designs and Intellectual Property Cores

• US 20080061980A1
• Filed: 09/07/2007
• Published: 03/13/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Algotronix Ltd.
• Original Assignee: Algotronix Ltd.
• Inventors: Kean, Thomas
• Granted Patent: US 8,063,739 B2
• Time in Patent Office: Days
• US Class Current: 340/572.1
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H04K 1/02 by adding a second signal to make the desired signal unintelligible

Abstract

In an embodiment of the invention, an active security tag is e bedded within the digital logic of an electronic design for logic destined for an integrated circuit such as an FPGA. The security tag includes security tag data which permits identification of the electronic design, and facilitates efforts to enforce copyrights in the designs. The security tag also includes a transmitter designed to covertly transmit security tag data to a receiver. Other information, such as error information and status information about the integrated circuit may also be transmitted. The transmitted information is concealed from detection by being hidden within background noise signals or other signals created by normal usage of the integrated circuit.

Claims

1. A security tag for an electronic design implemented on an integrated circuit, comprising:

Tag data which uniquely identifies the electronic design;

A communications channel for interfacing with an external detector, to deliver the tag data to the external detector; and

A transmitter for transmitting the tag data using a tag data signal via the communications channel to the external detector;

2. The security tag of claim 1, wherein the security tag comprises a design fragment incorporated into an intellectual property core stored on the integrated circuit.

3. The security tag of claim 1, wherein the security tag comprises a circuit within the integrated circuit.

4. The security tag of claim 1, further comprising a data link connected to the integrated circuit containing the security tag, the data link for providing information from the integrated circuit to the security tag, the information for transmission by the transmitter via the communications channel to the external detector.

5. The security tag of claim 4, wherein the information comprises error information.

6. The security tag of claim 1, further comprising a coding module for coding the tag data into the tag data signal for transmission by the transmitter.

7. The security tag of claim 6, wherein the coding module comprises a signal amplifier to amplify the tag data signal.

8. The security tag of claim 6, wherein the coding module comprises a signal mixer to mix the tag data signal with a carrier frequency.

9. The security tag of claim 6, wherein the coding module comprises a frequency hopper for changing a transmission frequency used by the transmitter to transmit the tag data signal.

10. The security tag of claim 1, further comprising a spreading circuit for spreading the tag data signal using a spreading code, and a ring oscillator for providing a carrier frequency and a clock signal to the spreading circuit, and wherein the transmitter comprises a high fan out net for creating a voltage disturbance on a power supply connection, the voltage disturbance comprising the tag data and the power supply connection comprising the communications channel.

11. The security tag of claim 1, wherein the communications channel comprises a power supply connection to a power supply pin of the integrated circuit containing the security tag;

wherein the external detector is connected to the power supply pin, and wherein the transmitter is for transmitting the tag data via the power supply connection and the power supply pin to the external detector.

12. The security tag of claim 1, wherein the external detector comprises an antenna, the communications channel comprises an EMI signal wave for interfacing with the antenna, and the transmitter comprises an EMI signal generator.

13. The security tag of claim 1, wherein the communications channel comprises an output pin on the integrated circuit containing the security tag and the transmitter comprises a timing modulator for modulating timing of an edge of a signal on the output pin, the modulation of the edge being used to encode the tag data for transmission.

14. The security tag of claim 1, wherein the communications channel comprises a thermal signal output from the integrated circuit containing the security tag;

the external detector comprises a temperature detector;

the transmitter comprises a power consumption modulator for modulating power consumption over time to generate modulations in the thermal signal output, the modulation in thermal signal output being used to encode the tag data for transmission.

15. The security tag of claim 1, further comprising a cryptographic key for encrypting the tag data signal.

16. The security tag of claim 1, wherein the communications channel comprises a covert communications channel, wherein the tag data signal is concealed from detection.

17. The security tag of claim 16, wherein the tag data signal is embedded within an interfering signal, wherein the interfering signal comprises a background noise signal generated during operation of the integrated circuit containing the security tag.

18. The security tag of claim 1, wherein the transmitter comprises a digital logic circuit implemented in the integrated circuit.

19. A method for detecting falsely labelled integrated circuits, comprising:

Reading tag data from a security tag, the security tag comprising tag data which uniquely identifies the electronic design;

A communications channel for interfacing with an external detector, to deliver the tag data to the external detector; and

a transmitter for transmitting the tag data using a tag data signal via the communications channel to the external detector;

Comparing the tag data with a product marking associated with the integrated circuit.

20. A method for enforcing electronic design tool licenses, comprising:

Causing an electronic design tool to covertly insert a security tag into a user design, wherein the security tag comprises a digital logic circuit including a transmitter implemented in the user design, and wherein the user design is implemented in an integrated circuit; and

Determining whether the security tag is present within the integrated circuit, using an external detection circuit to read tag data transmitted from the security tag by the transmitter.

21. A method for determining design version information on a user design programmed into an FPGA integrated circuit, comprising:

Receiving the FPGA integrated circuit, wherein the FPGA integrated circuit comprises a security tag, the security tag comprising information identifying a design and a transmitter for transmitting the information identifying the design, wherein the transmitter comprises a digital logic circuit implemented in the FPGA integrated circuit;

Causing the transmitter to transmit the information identifying the design; and

Determining the design version by reading the information transmitted by the transmitter, using an external detector.

22. A method for reading information from an integrated circuit, the integrated circuit comprising a security tag and a data link connected to the integrated circuit and to the security tag, the data link for providing the information from the integrated circuit to the security tag, the security tag comprising a communications channel for interfacing with an external detector, to deliver the information to the external detector, and a transmitter for transmitting the information using an information signal via the communications channel to the external detector, comprising:

Causing the integrated circuit to begin operating;

Causing the integrated circuit to deliver the information to the security tag over the data link;

Causing the transmitter to transmit the information over the communications channel to the external detector; and

Reading the information using the external detector.

23. The method of claim 22, wherein the information comprises error or status information about the operation of the integrated circuit.

24. The method of claim 22, wherein the transmitter comprises a digital logic circuit implemented in the integrated circuit.