DEVICE TEST AND DEBUG USING POWER AND GROUND TERMINALS

• US 20080065934A1
• Filed: 09/12/2007
• Published: 03/13/2008
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee
• Granted Patent: US 7,546,501 B2
• Time in Patent Office: Days
• US Class Current: 714/701
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31722 Addressing or selecting of test units, e.g. transmission protocols for selecting test units for scan test G01R31/318558
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

The present disclosure describes a novel method and apparatus for using a device'"'"'s power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Claims

1. A process of testing an integrated circuit having functional circuitry and test circuitry connected to the functional circuitry, the test circuitry having test input leads receiving test signals for testing the functional circuitry and a test output lead for sending response signals from the testing, the integrated circuit having power and ground leads, comprising:

A. receiving on a power lead of the integrated circuit modulated test control signals;

B. demodulating the test control signals;

C. formatting the demodulated test control signals;

D. applying the formatted test control signals to the fixed test input leads.

2. A process of testing an integrated circuit having functional circuitry and test circuitry connected to the functional circuitry, the test circuitry having test input leads receiving test signals for testing the functional circuitry and a test output lead for sending response signals from the testing, the integrated circuit having power and ground leads, comprising:

A. receiving test response signals from the test output lead;

B. formatting the test response signals;

C. modulating the formatted test response signals; and

D. applying the modulated and formatted test control signals to a power lead of the integrated circuit.

3. An integrated circuit comprising:

A. functional terminals available to outside the integrated circuit;

B. power and ground terminals separate from the functional terminals;

C. functional circuitry having functional leads connected to all of the functional leads and power and ground leads connected to the power and ground terminals;

D. test circuitry, the test circuitry being connected to the functional circuitry and having test control leads for controlling the testing of the functional circuitry, the test control leads being free of the functional terminals;

E. test messaging and control circuitry having an input lead and having output leads connected to the test control leads;

F. demodulation circuitry having an input connected to a power terminal and an output connected to the input lead of the test messaging and control circuitry; and

G. filter circuitry connected between the input of the demodulation circuitry, the power lead of the functional circuitry, and a ground terminal.

4. An integrated circuit comprising:

A. functional terminals available to outside the integrated circuit;

B. power and ground terminals separate from the functional terminals;

C. functional circuitry having functional leads connected to all of the functional leads and power and ground leads connected to the power and ground terminals;

D. test circuitry, the test circuitry being connected to the functional circuitry and having test control leads for controlling the testing of the functional circuitry, the test control leads being free of the functional terminals;

E. test messaging and control circuitry having an output lead and having an input lead connected to the test control leads;

F. modulation circuitry having an output connected to a power terminal and an input connected to the output lead of the test messaging and control circuitry; and

G. filter circuitry connected between the output of the modulation circuitry, the power lead of the functional circuitry, and a ground terminal.

5. An electrical device comprising:

A. functional circuitry for performing the functionality of the device;

B. test circuitry for testing the functional circuitry;

C. a power terminal for supplying a voltage to the functional and test circuitry;

D. a ground terminal for supplying a ground to the functional and test circuitry; and

E. receiving circuitry having an input coupled to the power terminal and an output coupled to an input of the test circuitry, the receiving circuitry including formatting circuitry providing formatted test information to the test circuitry in response to receiving test information at the power terminal.

6. An electrical device comprising:

A. functional circuitry for performing the functionality of the device;

B. test circuitry for testing the functional circuitry;

C. a power terminal for supplying a voltage to the functional and test circuitry;

D. a ground terminal for supplying a ground to the functional and test circuitry; and

E. sending circuitry having an input coupled to an output of the test circuitry and an output coupled to the power terminal, the sending circuitry including formatting circuitry providing formatted test information to the receiving circuitry output in response to receiving test information from the test circuitry.

7. An electrical device comprising:

A. functional circuitry for performing the functionality of the device;

B. test circuitry for selectively testing the functional circuitry;

C. a power terminal for supplying a voltage to the functional and test circuitry;

E. identification circuitry having an input coupled to the power terminal and an output, the identification circuitry providing identification patterns to the output for selecting the test circuitry.

8. An electrical device comprising:

A. functional circuitry for performing the functionality of the device;

B. first test circuitry for selectively testing the functional circuitry;

C. second test circuitry for selectively testing the functional circuitry;

D. a power terminal for supplying a voltage to the functional and test circuitry;

E. a ground terminal for supplying a ground to the functional and test circuitry; and

F. test selector and adaptor circuitry having an input coupled to the power terminal and an output connected to the test circuitry, the test selector and adaptor circuitry selectively providing test information to at least one of the first and second test circuitry.

9. A process of receiving serial test information comprising:

A. being in a message idle state in which no information is being received;

B. receiving message header information, the message header information including a start field, an identification field, and a command field; and

C. receiving message trailer information, the message trailer information including a code validating the correctness of the received message information, and a stop field indicating return to the message idle state.

10. A process of receiving serial test information comprising:

A. being in a message idle state in which no information is being received;

B. receiving message header information, the message header information including a start field, an identification field, a command field, and a packet number field;

C. receiving message payload information, the message payload information including packets of test information; and

D. receiving message trailer information, the message trailer information including a code field validating the correctness of the received message information, and a stop field indicating return to the message idle state.

11. A process of receiving serial test information comprising:

A. being in a message idle state in which no information is being received;

B. receiving message header information, the message header information including a start field, an identification field, and a command field;

D. receiving message trailer information, the message trailer information including a code validating the correctness of the received message information, and a stop field; and

E. sending acknowledge message information, the acknowledge message information including a start field, an identification field, a code field validating the correctness of the acknowledge message information, and a stop field indicating return to the message idle state.

12. A process of sending serial test information comprising:

A. being in a message idle state in which no information is being sent;

B. sending message header information, the message header information including a start field, an identification field, and a command field; and

D. sending message trailer information, the message trailer information including a code validating the correctness of the sent message information, and a stop field.

13. A process of sending serial test information comprising:

A. being in a message idle state in which no information is being sent;

B. sending message header information, the message header information including a start field, an identification field, a command field, and a packet number field;

C. sending message payload information, the message payload information including packets of test information; and

D. sending message trailer information, the message trailer information including a code field validating the correctness of the received message information, and a stop field indicating return to the message idle state.

14. A process of sending serial test information comprising:

A. being in a message idle state in which no information is being sent;

B. sending message header information, the message header information including a start field, an identification field, and a command field;

D. sending message trailer information, the message trailer information including a code validating the correctness of the received message information, and a stop field; and

E. receiving acknowledge message information, the acknowledge message information including a start field, an identification field, a code field validating the correctness of the acknowledge message information, and a stop field indicating return to the message idle state.