METHOD FOR FABRICATING A TRENCH STRUCTURE, AND A SEMICONDUCTOR ARRANGEMENT COMPRISING A TRENCH STRUCTURE

• US 20080067626A1
• Filed: 08/06/2007
• Published: 03/20/2008
• Est. Priority Date: 08/10/2006
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schulze, Hans-Joachim, Hirler, Franz, Strack, Helmut, Mauder, Anton, Kautzsch, Thoralf, Rueb, Michael, Willmeroth, Armin
• Application Number:
  US11/834,154
• Publication Number:
  US 20080067626A1
• Time in Patent Office: Days
• US Class Current: 257/501
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode

Abstract

A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.

Claims

1. A method for fabricating a semiconductor device comprising:

a) producing a first trench section proceeding from a surface of a semiconductor body into the semiconductor body;

b) producing a semiconductor layer above the surface and above the first trench section; and

c) producing a further trench section in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.

2. The method of claim 1, comprising:

d) repeating steps b) and c) until the trench structure has reached a desired depth T′

.

3. The method of claim 1, wherein the semiconductor layer is produced epitaxially.

4. The method of claim 1, wherein the semiconductor layer is produced with a thickness of between 1 μ

m and 12 μ

m, in particular between 1 μ

m and 6 μ

m.

5. The method of claim 1, wherein the trench structure is formed with a depth T′

of at least 10 μ

m.

6. The method of claim 1, wherein the semiconductor layer is produced from the same semiconductor material as the semiconductor body.

7. The method of claim 1, wherein the semiconductor layer is doped during or after production.

8. The method of claim 7, wherein the doping is varied in a lateral and/or vertical direction.

9. The method of claim 1, wherein each trench section is produced with a uniform width B.

10. The method of claim 1, wherein the trench sections are in each case produced by an etch.

11. The method of claim 1, wherein each trench section is at least partly filled with filling material.

12. The method of claim 11, wherein a dielectric is at least partly used as filling material.

13. The method of claim 12, wherein a high-k material is at least partly used as dielectric.

14. The method of claim 1, wherein trench sections lying one above another at least partly overlap.

15. The method of claim 1, wherein, before producing the semiconductor layer, a layer is produced parallel to the surface of the semiconductor body and patterned in such a way that a connecting element is formed, which connects two trench sections lying one above another to one another.

16. The method of claim 1, wherein, before producing the semiconductor layer, a layer is produced parallel to the surface of the semiconductor body and patterned in such a way that a connecting element is formed, which connects two laterally spaced-apart trench sections lying one above another to one another.

17. The method of claim 15, wherein the layer is produced with a thickness equal to the width of the trench sections.

18. The method of claim 15, wherein the connecting element is configured like the trench sections to be connected.

19. The method of claim 15, wherein the semiconductor layer is produced by selective growth at least at the beginning of production.

20. The method of claim 1, wherein the semiconductor device is a TEDFET.

21. A semiconductor arrangement comprising:

a trench structure, wherein the trench structure is composed of

a plurality of vertical trench sections, and

at least one lateral connecting element.

22. The semiconductor arrangement of claim 21, wherein the semiconductor arrangement has a plurality of semiconductor layers lying one above another.

23. The semiconductor arrangement of claim 22, wherein the semiconductor layers are epitaxial layers.

24. The semiconductor arrangement of claim 21, wherein a first vertical trench section is arranged in a first semiconductor layer and a second vertical trench section is arranged in a second semiconductor layer arranged above the first semiconductor layer.

25. The semiconductor arrangement of claim 24, wherein the connecting element is arranged between the first and the second semiconductor layer.

26. The semiconductor arrangement of claim 21, wherein the trench sections and the at least one connecting element are configured identically in kind.

27. The semiconductor arrangement of claim 21, wherein the trench structure is filled.

28. The semiconductor arrangement of claim 27, wherein the trench structure is at least partly filled with a dielectric.

29. The semiconductor arrangement of claim 21, wherein the semiconductor arrangement forms a TEDFET.

30. The semiconductor arrangement of claim 29, wherein the trench structure separates a drift control zone in the semiconductor arrangement from a drift zone in the semiconductor arrangement.

31. The semiconductor arrangement of claim 30, wherein a quotient of a net dopant charge of the drift control zone in a semiconductor section adjoining the trench structure and the drift zone and the area of the trench structure arranged between the drift control zone and the drift zone is less than the breakdown charge of the drift control zone.