Field programmable gate array utilizing dedicated memory stacks in a vertical layer format

• US 20080074144A1
• Filed: 08/31/2007
• Published: 03/27/2008
• Est. Priority Date: 01/17/2002
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Inventors: Carlson, Randolph, Boyd, W., Leon, John, Gann, Keith, Ozguz, Volkan
• Granted Patent: US 7,649,386 B2
• Time in Patent Office: Days
• US Class Current: 326/47
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Claims

1. An electronic module comprising:

a field programmable gate array (FPGA);

an access lead network electrically coupled and proximate to the FPGA;

at least one memory stack external of said FPGA and electrically coupled to said access lead network, said memory stack defining at least one planar surface and comprised of a plurality of layers wherein each of said layers comprises at least one memory IC;

said memory stack further comprising at least one conductive I/O pad on said at least one planar surface for the routing of an electrical signal between said at least one memory IC and said access lead network;

wherein said module is comprised of a plurality of vertically stacked prepackaged IC chips.

2. An electronic module comprising:

a field programmable gate array (FPGA);

an access lead network electrically coupled and proximate to the FPGA;

at least one memory stack external of said FPGA and electrically coupled to said access lead network, said memory stack defining at least one planar surface and comprised of a plurality of layers wherein each of said layers comprises at least one memory IC;

said memory stack further comprising at least one conductive I/O pad on said at least one planar surface for the routing of an electrical signal between said at least one memory IC and said access lead network;

wherein said module is comprised of a plurality of vertically stacked neo-chips.