SYSTEMS AND APPARATUS WITH PROGRAMMABLE MEMORY CONTROL FOR HETEROGENEOUS MAIN MEMORY
First Claim
1. A main memory comprising:
- a memory controller having one or more memory channel interfaces to couple to one or more respective memory channels;
a memory channel having a memory channel bus coupled to one memory channel interface of the memory controller; and
wherein the memory controller capable of controlling accesses to at least one dynamic random access memory module and at least one non-volatile memory module coupled to the memory channel bus.
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Accused Products
Abstract
A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.
199 Citations
16 Claims
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1. A main memory comprising:
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a memory controller having one or more memory channel interfaces to couple to one or more respective memory channels;
a memory channel having a memory channel bus coupled to one memory channel interface of the memory controller; and
wherein the memory controller capable of controlling accesses to at least one dynamic random access memory module and at least one non-volatile memory module coupled to the memory channel bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer system comprising:
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a printed circuit board including a plurality of traces;
at least one processor coupled to some of the plurality of traces of the printed circuit board;
a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the printed circuit board, the plurality of sockets to receive a plurality of different types of memory modules; and
a memory controller coupled between the at least one processor and the heterogeneous memory channel, the memory controller to control access to the plurality of different types of memory modules in the heterogeneous memory channel. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16-59. -59. (canceled)
Specification