SYSTEMS AND APPARATUS WITH PROGRAMMABLE MEMORY CONTROL FOR HETEROGENEOUS MAIN MEMORY

• US 20080082766A1
• Filed: 09/28/2007
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Virident Systems, LLC (Western Digital Corporation)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Okin, Kenneth, Karamcheti, Vijay, Parekh, Rajesh, Ganapathy, Kumar, Moussa, George
• Granted Patent: US 8,051,253 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Claims

1. A main memory comprising:

a memory controller having one or more memory channel interfaces to couple to one or more respective memory channels;

a memory channel having a memory channel bus coupled to one memory channel interface of the memory controller; and

wherein the memory controller capable of controlling accesses to at least one dynamic random access memory module and at least one non-volatile memory module coupled to the memory channel bus.

2. The main memory of claim 1, wherein

the memory controller is a programmable heterogeneous memory controller to flexibly adapt the memory channel interface to communicate with a memory module in response to the type of memory module being accessed.

3. The main memory of claim 1, wherein

communication to the memory channel bus is specified in a standard specification, and

the at least one non-volatile memory module is a translating memory module including a translator to translate standard specification data and instructions into data and instructions for a non-volatile memory integrated circuit.

4. The main memory of claim 2, wherein

the programmable heterogeneous memory controller is packaged into an integrated circuit package with a processor compatible pinout to couple into a processor socket.

5. The main memory of claim 2, wherein

the programmable heterogeneous memory controller is co-packaged into an integrated circuit package with a processor to couple into a processor socket.

6. The main memory of claim 1, wherein

the channel further includes

at least one socket coupled to the memory channel bus, the at least one socket capable of receiving the at least one dynamic random access memory module;

and

at least one other socket coupled to the memory channel bus, the at least one other socket capable of receiving the at least one non-volatile memory module.

7. The main memory of claim 6, wherein

the memory channel bus includes

one or more point to point wires independently coupled between the memory controller and each respective socket, and

a plurality of bus wires coupled to the memory controller and every socket in the memory channel.

8. The main memory of claim 7, wherein

one of the one or more point to point wires is assigned to be a feedback control signal from each memory module to the memory controller.

9. A computer system comprising:

a printed circuit board including a plurality of traces;

at least one processor coupled to some of the plurality of traces of the printed circuit board;

a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the printed circuit board, the plurality of sockets to receive a plurality of different types of memory modules; and

a memory controller coupled between the at least one processor and the heterogeneous memory channel, the memory controller to control access to the plurality of different types of memory modules in the heterogeneous memory channel.

10. The computer system of claim 9, wherein

the memory controller is a programmable heterogeneous memory controller to flexibly adapt the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

11. The computer system of claim 9, wherein

one memory module that is coupled to one socket in the heterogeneous memory channel is a random access memory module, and

another memory module that is coupled to another socket in the heterogeneous memory channel is a non-volatile memory module.

12. The computer system of claim 11, wherein

the random access memory module is a dynamic random access memory module.

13. The computer system of claim 11, wherein

the random access memory module is a static random access memory module.

14. The computer system of claim 9, wherein

the memory controller is an integrated memory controller integrated with at least one processor on a silicon die and coupled into a processor socket mounted to the printed circuit board.

15. The computer system of claim 9, wherein

each of the plurality of different types of memory modules has a memory module identification to indicate the type of memory module coupled into the plurality of sockets of the heterogeneous memory channel.

16-59. -59. (canceled)