Area Optimized Full Vector Width Vector Cross Product

• US 20080082784A1
• Filed: 10/26/2007
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam James, Mejdrich, Eric Oliver, Tubbs, Matthew Ray
• Application Number:
  US11/925,064
• Publication Number:
  US 20080082784A1
• Time in Patent Office: Days
• US Class Current: 712/4
• CPC Class Codes: G06T 15/06 Ray-tracing
• CPC Class Codes: G06T 2200/28 involving image processing hardware

Abstract

The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

Claims

1. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

a processor comprising;

a first vector unit; and

a second vector unit,

wherein the first vector unit and the second vector unit each comprise a plurality of processing lanes configured to execute an instruction, wherein one or more resources in one or more processing lanes of the second vector unit are shared with the first vector unit to execute a cross product instruction.

2. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the processor.

3. The design structure of claim 1, wherein the design structure resides on the storage medium as a data format used for the exchange of layout data of integrated circuits.

4. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

5. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

a system, comprising a plurality of processors communicably coupled with one another, wherein each processor comprises;

a first vector unit; and

a second vector unit,

wherein the first vector unit and the second vector unit each comprise a plurality of processing lanes configured to execute an instruction, wherein one or more resources in one or more processing lanes of the second vector unit are shared with the first vector unit to execute a cross product instruction.

6. The design structure of claim 5, wherein the design structure comprises a netlist, which describes the system.

7. The design structure of claim 5, wherein the design structure resides on the storage medium as a data format used for the exchange of layout data of integrated circuits.

8. The design structure of claim 5, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.