Soft-Input Soft-Output Decoder for Nonvolatile Memory

• US 20080082897A1
• Filed: 09/28/2006
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Conley, Kevin M., Brandman, Yigal
• Granted Patent: US 7,904,783 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Claims

1. A nonvolatile memory system comprising:

a memory array including a plurality of cells that store a plurality of data bits and a plurality of parity bits that are calculated from the plurality of data bits according to an encoding scheme;

a demodulator that reads the plurality of cells and derives raw likelihood values corresponding to the plurality of data bits and the plurality of parity bits; and

a decoder that receives the raw likelihood values and calculates output likelihood values therefrom using the encoding scheme.

2. The nonvolatile memory system of claim 1 wherein the demodulator resolves a number of read states per cell that is greater than the number of program states used to program the plurality of cells.

3. The nonvolatile memory system of claim 1 wherein the decoder subsequently calculates additional likelihood values from the output likelihood values using the encoding scheme.

4. The nonvolatile memory system of claim 3 wherein the decoder calculates additional likelihood values in two or more iterations, the iterations performed until a predetermined condition is met.

5. The nonvolatile memory system of claim 4 further comprising a hard-input hard-output decoder.

6. The nonvolatile memory system of claim 1 wherein the encoding scheme uses turbo coding.

7. The nonvolatile memory system of claim 1 wherein the encoding scheme uses a Low Density Parity Check (LDPC) code.

8. The nonvolatile memory system of claim 1 further comprising a converter that converts a soft input to a hard output.

9. A nonvolatile memory system comprising:

a nonvolatile memory array that stores two or more bits in an individual memory cell; and

a demodulator that derives an individual likelihood value for each of the two or more bits stored in the individual memory cell.

10. The nonvolatile memory system of claim 9 further comprising a lookup table that is used to obtain the individual likelihood values for each of the two or more bits.

11. The nonvolatile memory system of claim 9 wherein the two or more bits include at least one parity bit that was added according to an encoding scheme.

12. The nonvolatile memory system of claim 9 wherein the demodulator derives the individual likelihood values by reading the individual memory cell with a resolution that identifies more than the number of program states of the individual memory cell.

13. The nonvolatile memory system of claim 9 further comprising a soft-input soft-output decoder that receives the individual likelihood values as input and calculates output likelihood values from the individual likelihood values.

14. The nonvolatile memory system of claim 9 wherein the demodulator reads the individual memory cell using a predetermined pattern of read operations, the pattern having at least one area of higher density and one area of lower density.

15. A nonvolatile memory system comprising:

an array of nonvolatile memory cells that are individually programmed to one of two or more threshold voltage ranges that represent two or more states; and

a demodulator that resolves an individual cell threshold voltage to an identified one of the two or more threshold voltage ranges and further resolves the individual cell threshold voltage within the identified threshold voltage range by providing a higher density of read operations for a first portion of the identified threshold voltage range than at for a second portion of the identified threshold voltage range, the demodulator deriving likelihood values from the read operations for the first and second portions.

16. The nonvolatile memory system of claim 15 further comprising a soft-input soft-output decoder that receives the likelihood values as input.

17. The nonvolatile memory system of claim 16 wherein the soft-input soft-output decoder calculates output likelihood values in multiple iterations until a predetermined condition is met.

18. The nonvolatile memory system of claim 17 further comprising a soft-hard converter that converts the output likelihood values to hard output values when the predetermined condition is met.

19. The nonvolatile memory system of claim 17 further comprising a hard-input hard-output decoder that receives the output likelihood values from the soft-input soft-output decoder, the hard-input hard-output decoder determining when the predetermined condition is met.

20. The nonvolatile memory system of claim 15 wherein nonvolatile memory cells are individually programmed to four or more threshold voltage ranges that represent four or more states to store two or more bits, the demodulator deriving likelihood values for each of the two or more bits.