Post passivation interconnection schemes on top of IC chips
First Claim
1. A method for fabricating a chip, comprising:
- providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second metal layers, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost nitride layer of said chip and a topmost oxide layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and
forming a second metallization structure in said second opening and over said polymer layer, wherein said forming said second metallization structure comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer.
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Accused Products
Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
69 Citations
20 Claims
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1. A method for fabricating a chip, comprising:
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providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second metal layers, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost nitride layer of said chip and a topmost oxide layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and
forming a second metallization structure in said second opening and over said polymer layer, wherein said forming said second metallization structure comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for fabricating a chip, comprising:
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providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, and wherein said first metallization structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second metal layers, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost nitride layer of said chip and a topmost oxide layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and
forming a second metallization structure in said second opening and over said passivation layer, wherein said forming said second metallization structure comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method for fabricating a chip, comprising:
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providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, wherein said first pad has a size between 0.5 and 30 micrometers, and wherein said first metallization structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second metal layers, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost nitride layer of said chip and a topmost oxide layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and
forming a second metallization structure in said second opening and over said passivation layer, wherein said forming said second metallization structure comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification