Display controller

• US 20080094413A1
• Filed: 10/24/2006
• Published: 04/24/2008
• Est. Priority Date: 10/24/2006
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Emerson, Theodore F., Autor, Jeffrey S.
• Granted Patent: US 8,922,585 B2
• Time in Patent Office: Days
• US Class Current: 345/629
• CPC Class Codes: G06F 11/0769 Readable error formats, e.g. cross-platform generic formats, human understandable formats
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2330/026 Arrangements or methods related to booting a display
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

Systems, methods, and other embodiments associated with a display controller are described. One display controller embodiment includes a data store to store overlay control data, a port to communicate with an overlay control data provider, and a logic to provide an overlay to a display device. The display device may be associated with a computing system that does not provide the overlay control data. The logic may be controlled by the overlay control data provider.

Claims

1. A display controller apparatus, comprising:

a data store to store an overlay control data;

a port to communicate with a provider of the overlay control data; and

a logic to provide an overlay to a display device associated with a computing system to which the display controller provides a display service and that is not the provider of the overlay control data, the overlay being an image that can be displayed on the display device, the logic being controlled, at least in part, by the provider of the overlay control data, the overlay being described by the overlay control data, the overlay being rendered by the provider of the overlay control data.

2. The apparatus of claim 1, where the overlay can be displayed on the display device one or more of, at the same time as an image provided to the display device by the computing system, and independently of an image provided by the computing system.

3. The apparatus of claim 1, where the display controller is not initialized by the computing system, and where the provider of the overlay control data is not initialized by the computing system.

4. The apparatus of claim 1, the overlay control data comprising one or more of, an overlay position data, an overlay size data, an overlay frame address, an overlay intensity data, an overlay transparency data, and an overlay pre-emption data.

5. The apparatus of claim 1, the port being one of, a bi-directional communication port, an I2C (Inter-integrated Circuit) port, and an SPI (Serial Peripheral Interface) port.

6. The apparatus of claim 1, the provider of the overlay control data being a management processor that is part of a management infrastructure.

7. The apparatus of claim 1, where the logic can provide the overlay to the display device independent of a state of the computing system, the state comprising one or more of, a boot state, an operating system state, an application state, a failure state, and a power state.

8. The apparatus of claim 7, where the logic can provide the overlay to the display device without consuming a resource of the computing system, the resource comprising one or more of, a processor cycle, a memory location, an operating system action, and an application action.

9. The apparatus of claim 1, including a VRAM (video random access memory) that is writeable by both the display controller and the provider of the overlay control data.

10. The apparatus of claim 9, including the computing system and the display device.

11. The apparatus of claim 1, where the provider of the overlay control data interrogates the display device for one or more of, a preferred operating mode, and a possible operating mode, and where the provider of the overlay control data initializes the data store based, at least in part, on one or more of, the preferred operating mode, and the possible operating mode.

12. The display controller apparatus of claim 1, the display controller apparatus being configured as a video controller comprising:

one or more registers to store the overlay control data; and

where the logic is configured to provide a first image to the display device, the first image being characterized, at least in part, by the overlay control data;

a management subsystem comprising;

a processor to write one or more values to the one or more registers to control the logic; and

a shared memory controller operably connected to the video controller, to the management subsystem, and to a memory in which the first image may be stored;

the video controller being initialized, at least in part, by the processor.

13. The system of claim 12, where the first image may appear one or more of, independently on the display device, and along with a second image provided to the display device by a computing system to which the video controller provides a video service, the first image overlaying the second image.

14. The system of claim 12, where the management subsystem renders the first image into the memory accessible through the shared memory controller.

15. The system of claim 12, where the one or more registers come out of a reset state in a pre-determined useable state.

16. The system of claim 13, the logic overlaying the first image on the display device independent of a state of the computing system, the state comprising a boot state, an operating system state, an application state, a failure state, and a power state, and the logic overlaying the first image on the display device without consuming a resource of the computing system, the resource comprising a processor cycle, a memory location, an operating system action, and an application action.

17. A method, comprising:

initializing at least a portion of a video controller that is operably connected to a display device and to a computing system for which the video controller provides a video service, where the initializing is performed by a management processor operably connected to the computing system, and where the initializing is performed independent of the computing system;

rendering a display element in a memory operably connected to the video controller, where the rendering is performed by the management processor; and

controlling the video controller to overlay the display element on the display device, where the controlling is performed by the management processor.

18. The method of claim 17, the display element comprising a popup message concerning one or more of, information concerning the computing system, and information concerning a management processor action.

19. The method of claim 17, including controlling the video controller to overlay the display element independent of a state of the computing system, the state comprising a boot state, an operating system state, an application state, a failure state, and a power state, and controlling the video controller to overlay the display element without consuming a resource of the computing system, the resource comprising a processor cycle, a memory location, an operating system action, and an application action, and

where controlling the video controller includes establishing one or more of, a display element position, a display element size, a display element shape, a display element intensity, a display element transparency, and a display element pre-emption status.

20. The method of claim 17, where rendering a display element in the memory operably connected to the video controller includes rendering the display element into a first set of memory in the memory, where write access to the first set of memory is granted to the management processor and where write access to the first set of memory is not granted to the computing system.