PROCESSOR ACQUISITION OF OWNERSHIP OF ACCESS COORDINATOR FOR SHARED RESOURCE

• US 20080098180A1
• Filed: 10/23/2006
• Published: 04/24/2008
• Est. Priority Date: 10/23/2006
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Johnson, Robert, Larson, Douglas
• Granted Patent: US 7,861,042 B2
• Time in Patent Office: Days
• US Class Current: 711/150
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Claims

1. An apparatus, comprising:

a processor that upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator, wherein upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

2. The apparatus of claim 1, wherein the processor, upon the failure of the earlier attempt to directly acquire ownership of the access coordinator, locally determines the amount to delay the later attempt to directly acquire ownership of the access coordinator, wherein upon an occurrence of the failure of the later attempt to directly acquire ownership of the access coordinator the processor would enter into the indirect waiting arrangement for ownership of the access coordinator.

3. The apparatus of claim 1, wherein the processor, upon the failure of the earlier attempt to directly acquire ownership of the access coordinator for the resource, locally determines the amount to delay the later attempt to directly acquire ownership of the access coordinator;

wherein the processor, upon the failure of the later attempt to directly acquire ownership of the access coordinator, locally determines an amount to delay the subsequent attempt to directly acquire ownership of the access coordinator, wherein upon an occurrence of the failure of the subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into the indirect waiting arrangement for ownership of the access coordinator.

4. The apparatus of claim 1, wherein the access coordinator for the resource comprises one or more spinlocks and/or one or more blocking locks on the resource.

5. The apparatus of claim 4, wherein a plurality of processors comprises the processor and the one or more additional processors, wherein the plurality of processors operates under a modified ticket-serving with prearbitration arrangement;

wherein the processor locally determines the amount to delay the later attempt to directly acquire ownership of the access coordinator through employment of a proportional relationship between the amount and a difference between ticket and serving values for the processor on the access coordinator under the modified ticket-serving with prearbitration arrangement.

6. The apparatus of claim 1, wherein the access coordinator for the resource comprises a single spinlock on the resource.

7. The apparatus of claim 1, wherein the processor, upon success of the later attempt to directly acquire ownership of the access coordinator avoids one or more cache misses that would be associated with an occurrence of entry of the processor into the indirect waiting arrangement for ownership of the access coordinator.

8. The apparatus of claim 7, wherein the indirect waiting arrangement for ownership of the access coordinator comprises prearbitration for ownership of the access coordinator;

wherein the processor, upon success of the later attempt to directly acquire ownership of the access coordinator avoids one or more cache misses that would be associated with an occurrence of entry of the processor into the prearbitration for ownership of the access coordinator.

9. The apparatus of claim 1, wherein the processor heuristically determines the amount to delay the later attempt to directly acquire ownership of the access coordinator.

10. An apparatus, comprising:

a processor that locally determines an amount of delay for an attempt by the processor to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, wherein upon a completion of the amount of delay the processor adjusts a heuristic based on an occurrence of success or failure of the attempt to directly acquire ownership of the access coordinator, to adapt a later attempt by the processor to directly acquire ownership of the access coordinator.

11. The apparatus of claim 10, wherein the processor, upon an occurrence of the later attempt to acquire the ownership of the access coordinator, locally determines a different amount to delay a subsequent attempt to directly acquire ownership of the access coordinator.

12. The apparatus of claim 11, wherein the processor employs the heuristic to locally determine the different amount to delay the subsequent attempt to directly acquire ownership of the access coordinator.

13. The apparatus of claim 10, wherein the processor, upon a determination of unnecessary duration of preliminary ownership of the access coordinator, locally determines a reduced amount to delay a subsequent attempt to directly acquire ownership of the access coordinator.

14. The apparatus of claim 10, wherein the processor, upon a determination of premature attempt to acquire ownership of the access coordinator, locally determines an increased amount to delay a subsequent attempt to directly acquire ownership of the access coordinator.

15. The apparatus of claim 10, wherein the delay for the attempt by the processor to directly acquire ownership of the access coordinator comprises a first delay portion and a second delay portion;

wherein the processor, upon completion of the first delay portion, locally determines that additional waiting is beneficial and makes a determination of the second delay portion, wherein upon completion of the second delay portion the processor executes the later attempt to directly acquire ownership of the access coordinator.

16. The apparatus of claim 10, wherein one or more attempts by the processor to directly acquire ownership of the access coordinator comprise the attempt by the processor to directly acquire ownership of the access coordinator, wherein upon an occurrence of failure of the one or more attempts to directly acquire ownership of the access coordinator, the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

17. The apparatus of claim 10, wherein the access coordinator for the resource comprises one or more spinlocks, one or more read/write spinlocks, one or more blocking locks, one or more read/write blocking locks, one or more adaptive locks, one or more mutexes, one or more condition variables, and/or one or more semaphores on the resource.

18. An apparatus, comprising:

a computer operating system that coordinates ownership of a spinlock for a resource shared among a plurality of processors;

wherein upon an occurrence of owned status of the spinlock contemporaneous with a request for ownership of the spinlock by a plural set of processors of the plurality of processors, the computer operating system allows a plural subset number of processors of the plural set of processors to directly wait for ownership of the spinlock;

wherein the computer operating system causes one or more additional processors of the plural set of processors in excess of the plural subset number of processors, to indirectly wait for ownership of the spinlock.

19. The apparatus of claim 18, wherein upon an occurrence of owned status of the spinlock contemporaneous with a request for ownership of the spinlock by a single processor of the plurality of processors, the computer operating system allows the single processor to directly wait for ownership of the spinlock.

20. The apparatus of claim 19, wherein the plural subset number of processors comprises the single processor and multiple processors, wherein upon an occurrence of owned status of the spinlock contemporaneous with the single processor directly waiting for ownership of the spinlock and a request for ownership of the spinlock by the multiple processors and the one or more additional processors of the plural set of processors, the computer operating system allows the single processor and the multiple processors to directly wait for ownership of the spinlock and causes the one or more additional processors to indirectly wait for ownership of the spinlock.