FAST AUDIO AND ANGLE SWITCHING VIA MULTIPLE DEMUX BUFFERS
First Claim
1. A circuit for decoding data, said circuit comprising:
- a processor for demultiplexing a plurality of elementary streams from a multiplexed stream, wherein each of the plurality of elementary streams comprises portions, wherein each of the portions comprises time stamps;
a system clock for maintaining a clock reference;
a plurality of FIFOs corresponding to the plurality of elementary streams for queuing each of the plurality of elementary streams, wherein each of the plurality of FIFOs comprise a front end, and wherein the front end of each of the plurality of FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and
at least one decoder for decoding selected ones of the plurality of elementary streams by decoding portions at the front end of the FIFO corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of elementary streams by switching from decoding portions at the front end of a FIFO corresponding to one of the selected ones of the plurality of elementary streams to decoding portions at the front end of a FIFO corresponding to the newly selected one of the plurality of elementary streams.
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Accused Products
Abstract
Presented herein are system(s) and method(s) for fast audio and angle switching via multiple demux buffers. In one embodiment, there is presented a circuit for decoding data. The circuit comprises a processor, a system clock, a plurality of queues, and at least one decoder. The processor demultiplexes a plurality of elementary streams from a multiplexed stream, wherein each of the plurality of elementary streams include portions, wherein each of the portions include time stamps. The system clock maintains a clock reference. The plurality of FIFOs correspond to the plurality of elementary streams and FIFO each of the plurality of elementary streams, wherein each of the plurality of FIFOs include a front end, and wherein the front end of each of the plurality of FIFOs stores the portion of the corresponding FIFO that includes a time stamp that is proximate to the clock reference. The at least one decoder decodes selected ones of the plurality of elementary streams by decoding portions at the front end of the FIFO corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of elementary streams by switching from decoding portions at the front end of a FIFO corresponding to one of the selected ones of the plurality of elementary streams to decoding portions at the front end of a FIFO corresponding to the newly selected one of the plurality of elementary streams.
13 Citations
21 Claims
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1. A circuit for decoding data, said circuit comprising:
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a processor for demultiplexing a plurality of elementary streams from a multiplexed stream, wherein each of the plurality of elementary streams comprises portions, wherein each of the portions comprises time stamps; a system clock for maintaining a clock reference; a plurality of FIFOs corresponding to the plurality of elementary streams for queuing each of the plurality of elementary streams, wherein each of the plurality of FIFOs comprise a front end, and wherein the front end of each of the plurality of FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and at least one decoder for decoding selected ones of the plurality of elementary streams by decoding portions at the front end of the FIFO corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of elementary streams by switching from decoding portions at the front end of a FIFO corresponding to one of the selected ones of the plurality of elementary streams to decoding portions at the front end of a FIFO corresponding to the newly selected one of the plurality of elementary streams. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit for decoding data, said integrated circuit comprising:
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a transport processor for receiving a transport stream, said transport stream comprising a plurality of packets, each of the packets comprising a portion of one of a plurality video elementary streams and a plurality of audio elementary streams, an identifier identifying the one of the plurality video elementary streams and a plurality of audio elementary streams, and a time stamp, wherein said transport processor demultiplexes each of the plurality of video elementary streams and the plurality of audio elementary streams by demultiplexing the portions of the video elementary streams and the audio elementary streams; a system clock for maintaining a clock reference; a plurality of audio FIFOs corresponding to the plurality of audio elementary streams for queuing each of the plurality of audio elementary streams, wherein each of the plurality of audio FIFOs comprise a front end, and wherein the front end of each of the plurality of audio FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and a plurality of video FIFOs corresponding to the plurality of video elementary streams for queuing each of the plurality of video elementary streams, wherein each of the plurality of video FIFOs comprise a front end, and wherein the front end of each of the plurality of video FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference. - View Dependent Claims (8, 9, 10, 11)
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12. A method for decoding data, said method comprising:
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receiving a program stream, said program stream comprising a plurality of packs, each of the packs comprising a portion of one of a plurality video elementary streams and a plurality of audio elementary streams, an identifier identifying the one of the plurality video elementary streams and a plurality of audio elementary streams, and a time stamp; demultiplexing each of the plurality of video elementary streams and the plurality of audio elementary streams by demultiplexing the portions of the video elementary streams and the audio elementary streams; maintaining a clock reference; queuing each of the plurality of audio elementary streams in a plurality of audio FIFOs corresponding to the plurality of audio elementary streams, wherein each of the plurality of audio FIFOs comprise a front end, and wherein the front end of each of the plurality of audio FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; queuing each of the plurality of video elementary streams in a plurality of video FIFOs corresponding to the plurality of video elementary streams, wherein each of the plurality of video FIFOs comprise a front end, and wherein the front end of each of the plurality of video FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference. - View Dependent Claims (13, 14, 15, 16)
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17. An integrated circuit for decoding data, said integrated circuit comprising:
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a program processor for receiving a program stream, said program stream comprising a plurality of packs, each of the packs comprising a portion of one of a plurality video elementary streams and a plurality of audio elementary streams, an identifier identifying the one of the plurality video elementary streams and a plurality of audio elementary streams, and a time stamp, wherein said program processor demultiplexes each of the plurality of video elementary streams and the plurality of audio elementary streams by demultiplexing the portions of the video elementary streams and the audio elementary streams; a system clock for maintaining a clock reference; a plurality of audio FIFOs corresponding to the plurality of audio elementary streams for queuing each of the plurality of audio elementary streams, wherein each of the plurality of audio FIFOs comprise a front end, and wherein the front end of each of the plurality of audio FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and a plurality of video FIFOs corresponding to the plurality of video elementary streams for queuing each of the plurality of video elementary streams, wherein each of the plurality of video FIFOs comprise a front end, and wherein the front end of each of the plurality of video FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference. - View Dependent Claims (18, 19, 20, 21)
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Specification