Method for manufacturing a lower substrate of a liquid crystal display device

• US 20080113461A1
• Filed: 06/19/2007
• Published: 05/15/2008
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Ting, Chin-Kuo, Tung, Yi-Pin
• Granted Patent: US 7,439,090 B2
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 2201/48 Flattening arrangements
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A method for manufacturing a lower substrate of a liquid crystal display device is disclosed and more particularly, a method for manufacturing a color filter layer on a lower substrate is disclosed. This method is achieved by using a photosensitive insulating layer as a passivation layer or an overcoat of a thin film transistor to reduce the number of masks, or of photographic steps. The photosensitive insulating layer used in the method has the characteristics of both photoresist and passivation layers so as to protect a thin film transistor from moisture and oxygen. In addition, the number of masks, or of photographic steps used in this method can be further reduced by ink-jet printing a color filter layer or by half-tone mask technique.

Claims

1. A method for manufacturing a lower substrate of a liquid crystal display device, comprising:

(A) providing a substrate;

(B) forming plural transistors individually comprising a gate, a source, and a drain, wherein the gate is disposed on the substrate, at least one semiconductor layer and at least one gate insulating layer are sandwiched in between the gate and the source/drain, and the drain does not electrically connect to the source;

(C) forming on the substrate in sequence a first photosensitive insulating layer and a black matrix, wherein the first insulating layer and the black matrix are the same type of photoresist;

(D) patterning the first photosensitive insulating layer and the black matrix to cover the transistor regions, wherein the pattern of the first photosensitive insulating layer is the same as that of the black matrix;

(E) forming on the substrate in sequence a second insulating layer and a color filter layer, wherein the second insulating layer and the color filter layer are the same type of photoresist;

(F) patterning the second insulating layer and the color filter layer, and simultaneously forming a first contact hole corresponding to the drain, wherein the first contact layer extends through the second insulating layer and the color filter layer so as to expose the part drain;

(G) selectively repeating the steps (E) and (F); and

(H) forming a patterned transparent electrode layer on the substrate, which electrically connects to the drain.

2. The method as claimed in claim 1, wherein step (B) further comprises a step for forming plural connecting terminal regions each at least comprising a terminal line on the substrate, and the gate insulating layer is disposed on the terminal line.

3. The method as claimed in claim 2, wherein step (F) further comprises a step for simultaneously forming a second contact hole in the connecting terminal region, and the second contact hole at least extends through the second photosensitive insulating layer and the filter layer so as to expose part of the gate insulating layer.

4. The method as claimed in claim 3, further comprising step (G′

) between step (G) and step (H), dryly etching the exposed gate insulating layer so as to expose part of the terminal line.

5. The method as claimed in claim 1, wherein step (B) further comprises a step for forming plural connecting terminal regions each at least comprising a terminal line and a connecting line, the terminal line is disposed on the substrate, the gate insulating layer is sandwiched in between the terminal line and the connecting line, and the terminal line connects to the connecting line via a through hole.

6. The method as claimed in claim 5, wherein step (F) further comprises a step for forming a second contact hole in the connecting terminal region, and the second contact hole at least extends through the second photosensitive insulating layer and the filter layer so as to expose part of the connecting line.

7. The method as claimed in claim 1, wherein step (B) further comprises a step for forming plural auxiliary capacitance regions each at least comprising a lower electrode, a gate insulating layer, and an upper electrode, the lower electrode is disposed on the substrate, and the gate insulating layer is sandwiched in between the upper electrode and the lower electrode.

8. The method as claimed in claim 1, wherein the process for patterning the first photosensitive insulating layer and the black matrix of step (D) is performed by a mask, so as to expose and develop the first photosensitive insulating layer and the black matrix.

9. The method as claimed in claim 1, wherein the process for forming the color filter layer of step (F) is performed by spin coating.

10. The method as claimed in claim 1, wherein the process for forming the color filter layer of step (F) is performed by ink-jet printing.

11. The method as claimed in claim 1, wherein the color of the color filter layer corresponding to one of the transistors is different from that of the neighboring color filter layer corresponding to another of the transistors.

12. A method for manufacturing a lower substrate of a liquid crystal display device, comprising:

(A) providing a substrate;

(B) forming plural transistor regions individually having a gate, a source, and a drain, wherein the gate is disposed on the substrate, at least one semiconductor layer and at least one gate insulating layer are sandwiched in between the gate and the source/drain, and the drain does not electrically connect to the source;

(C) forming on the substrate in sequence a passivation layer, a black matrix, and a first photosensitive insulating layer;

(D) patterning the first photosensitive insulating layer and the black matrix to cover the transistor regions, wherein the pattern of the first photosensitive insulating layer is the same as that of the black matrix;

(E) forming on the substrate in sequence a second insulating layer and a color filter layer;

(F) patterning the second insulating layer and the color filter layer, and simultaneously forming a first contact hole in the second insulating layer and the color filter layer on the drain, wherein the first contact hole extends through the second insulating layer and the color filter layer so as to expose part of the passivation layer;

(G) selectively repeating steps (E) and (F);

(H) dryly etching the passivation layer in the first contact hole to expose part of the drain; and

(I) forming a patterned transparent electrode layer on the substrate, which electrically connects to the drain.

13. The method as claimed in claim 12, wherein step (B) further comprises a step for forming plural connecting terminal regions each at least comprising a terminal line on the substrate, and the gate insulating layer is sandwiched in between the terminal line and the passivation layer.

14. The method as claimed in claim 13, wherein step (F) further comprises a step for simultaneously forming a second contact hole in the connecting terminal region, and the second contact hole extends through the second photosensitive insulating layer and the color filter layer so as to expose part of the passivation layer.

15. The method as claimed in claim 14, wherein step (H) further comprises a step for dryly etching the passivation layer and the gate insulating layer in the second contact hole so as to expose part of the terminal line.

16. The method as claimed in claim 12, wherein step (B) further comprises a step for forming plural auxiliary capacitance regions each at least comprising a lower electrode, a gate insulating layer, and an upper electrode, the lower electrode is disposed on the substrate, and the gate insulating layer is sandwiched in between the upper electrode and the lower electrode.

17. The method as claimed in claim 12, wherein the process for patterning the first photosensitive insulating layer and the black matrix of step (D) is performed by a mask so as to expose and develop the first photosensitive insulating layer and the black matrix.

18. The method as claimed in claim 12, wherein the process for forming the color filter layer of step (F) is performed by spin coating.

19. The method as claimed in claim 12, wherein the process for forming the color filter layer of step (F) is performed by ink-jet printing.

20. The method as claimed in claim 12, wherein the color of the color filter layer corresponding to one of the transistor is different from that of the neighboring color filter layer corresponding to another of the transistors.