Semiconductor device with trench transistors and method for manufacturing such a device

• US 20080116511A1
• Filed: 11/16/2006
• Published: 05/22/2008
• Est. Priority Date: 11/16/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Zundel, Markus, Zelsacher, Rudolf, Bacher, Erwin
• Granted Patent: US 7,601,596 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches and on the first side. A part of the first side and the trenches is masked using a first mask, and the semiconductor material is doped by implantation through the thick oxide layer while the first mask is present. At least part of the thick oxide layer is removed while the first mask remains.

Claims

1-16. -16. (canceled)

17. A method for manufacturing a semiconductor device comprising:

forming trenches in a first side of a semiconductor material;

forming a thick oxide layer on the trenches and on the first side;

masking a part of the first side and the trenches using a first mask;

doping the semiconductor material by implantation through the thick oxide layer while the first mask is present; and

removing at least part of the thick oxide layer while the first mask remains.

18. The method as recited in claim 17 further comprising forming a thin oxide layer on the first side after the removing step.

19. The method as recited in claim 18 further comprising removing the first mask after the removing step and before the forming of the thin oxide layer step.

20. The method as recited in claim 18 wherein the forming of the thin oxide layer is a thermal treatment, the thermal treatment also expanding a section of the semiconductor material doped by the implantation.

21. The method as recited in claim 17 wherein the removing step including etching, a part of the thick oxide layer remaining underneath the first mask and also in the trenches.

22. The method as recited in claim 17 further comprising adding a conductive material into the trenches after the forming of the thick oxide layer and prior to the doping step.

23. The method as recited in claim 22 wherein the conductive material is doped polysilicon.

24. A method for manufacturing a semiconductor device comprising:

forming trenches in a first side of a semiconductor material, the trenches having a bottom;

forming a thick oxide layer on the first side of the semiconductor material and on the trenches;

adding a conductive material in the trenches over the thick oxide layer; and

doping the semiconductor material by implantation through the thick oxide layer, the trenches being covered by the thick oxide material and the conductive material so that the implantation avoids the trench bottom.

25. A method for manufacturing a semiconductor device comprising:

forming trenches in a first side of a semiconductor material, the trenches having a bottom;

forming a thick oxide layer on the first side of the semiconductor material and on the trenches;

removing at least a part of the thick oxide layer;

doping the semiconductor material by implantation to form a body region before or after the removing step; and

thermally treating the semiconductor material after the doping to both form a thin oxide layer over the body and to extend the body region.

26. A semiconductor device comprising:

a base semiconductor material with a first side and a second side, the semiconductor material including a plurality of trenches, each trench extending perpendicularly with respect to the first and second sides and having a trench top at the first side and a trench bottom, a plurality of said trenches having an end in the end direction, each end having a thick oxide layer at the trench top, and at least one trench having a thin oxide layer at the trench top away from the end beginning at a first location; and

a plurality of body regions located in the base semiconductor material between the trenches, each body region including a body region end in the end direction;

and at least one body region end next said at least one trench being a predetermined distance from the first location

27. The semiconductor device as recited in claim 26 wherein each trench has the thick oxide layer underneath the thin oxide layer.

28. The semiconductor device as recited in claim 26 wherein each body region includes two source terminals and a contact between the two source terminals.

29. The semiconductor device as recited in claim 26 wherein each trench includes a gate electrode.

30. The semiconductor device as recited in claim 26 wherein each trench further includes a field electrode between the gate electrode and the trench bottom, the thick oxide layer being located between the field electrode and the trench bottom.

31. The semiconductor device as recited in claim 30 wherein the thin oxide layer separates the gate electrode and the field electrode.

32. The semiconductor device as recited in claim 26 further comprising a first contact layer adjacent the first side and a second contact layer adjacent the second side.

33. The semiconductor device as recited in claim 26 wherein the device includes DMOS power transistors