SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20080116583A1
• Filed: 11/15/2007
• Published: 05/22/2008
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: YUKI, Kazuyoshi
• Granted Patent: US 7,713,828 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A semiconductor device includes a semiconductor substrate, source and drain regions on the semiconductor substrate, and contact plugs connected to the source and drain regions. The contact plugs includes first impurity-diffused epitaxial layers that contact with the source and drain regions.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

source and drain regions on the semiconductor substrate; and

contact plugs connected to the source and drain regions, the contact plugs including first impurity-diffused epitaxial layers that contact with the source and drain regions.

2. The semiconductor device according to claim 1, wherein each of the source and drain regions comprises:

a diffusion layer in the semiconductor substrate; and

a second impurity-diffused epitaxial layer over the diffusion layer, the second impurity-diffused epitaxial layer being positioned above the semiconductor substrate.

3. A method of forming a semiconductor device, the method comprising:

forming source and drain regions on a semiconductor substrate; and

forming contact plug impurity-diffused epitaxial layers over the source and drain regions, the contact plug impurity-diffused epitaxial layers serving as at least parts of contact plugs.

4. The method according to claim 3, wherein forming source and drain regions comprises:

forming diffusion layers in the semiconductor substrate; and

forming impurity-diffused epitaxial layers over the diffusion layers.

5. A method of forming a MOS transistor in an active region surrounded by an isolation film, the method comprising:

forming a gate insulating film on a first part of the active region;

forming a gate electrode on the gate insulating film;

forming diffusion layers in second parts of the active region, the second parts being different from the first part;

forming first epitaxial layers of silicon on the diffusion layers;

introducing a first impurity into the first epitaxial layers and form source and drain regions which comprise stacks of the first epitaxial layers and the diffusion layers;

forming an inter-layer insulator which covers the gate electrode and the source and drain regions;

forming contact holes in the inter-layer insulator, the contact holes reaching the source and drain regions;

forming second epitaxial layers of silicon in the contact holes, the second epitaxial layers contacting with the source and drain regions; and

introducing an impurity into the second epitaxial layers to form at least parts of contact plugs.