FPGA AND METHOD AND SYSTEM FOR CONFIGURING AND DEBUGGING A FPGA

• US 20080116919A1
• Filed: 11/21/2007
• Published: 05/22/2008
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Yu Dong, Liu, Qiang, Li, Yu, Lin, Guo Hui
• Granted Patent: US 7,882,465 B2
• Time in Patent Office: Days
• US Class Current: 324/754
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]

Abstract

The present invention provides a Field Programmable Gate Array (FPGA), a system for debugging a Field Programmable Gate Array, a method for debugging a Field Programmable Gate Array, a FPGA configuration data product and a method and system for configuring a FPGA. According to one aspect of the invention, there is provided a Field Programmable Gate Array (FPGA) having a logic unit under test and comprising: a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test, and obtain a probe signal at said probe point; and a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit it to outside.

Claims

1. A Field Programmable Gate Array including a logic unit under test, the Field Programmable Gate Array comprising:

a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test and obtain a probe signal at said probe point; and

a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit said high speed serial signal to outside the Field Programmable Gate Array.

2. The Field Programmable Gate Array according to claim 1, further comprising:

a probe signal transforming unit configured to transform said probe signal into a signal that matches said high speed serial transceiver when said probe signal does not match said high speed serial transceiver.

3. The Field Programmable Gate Array according to claim 2, wherein said probe signal transforming unit transforms width and clock of said probe signal.

4. The Field Programmable Gate Array according to claim 1, wherein said high speed serial transceiver also receives a stimulation signal, and said Field Programmable Gate Array further comprises:

a stimulation signal selecting unit configured to select a stimulation signal received by said high speed serial transceiver and apply it to said logic unit under test.

5. The Field Programmable Gate Array according to claim 4, further comprising a stimulation signal transforming unit configured to transform said stimulation signal into a signal that matches said stimulation signal selecting unit when said stimulation signal received by said high speed serial transceiver does not match said stimulation signal selecting unit.

6. The Field Programmable Gate Array according to claim 5, wherein said stimulation signal transforming unit transforms width and clock of said stimulation signal.

7. The Field Programmable Gate Array according to claim 1, wherein said high speed serial transceiver converts the high speed serial signal into a low speed parallel signal.

8. A system for debugging Field Programmable Gate Arrays, the system comprising:

a Field Programmable Gate Array including;

a) a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test and obtain a probe signal at said probe point; and

b) a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit said high speed serial signal to outside the Field Programmable Gate Array; and

an analyzing means configured to receive and analyze a signal sent by said high speed serial transceiver.

9. The system for debugging Field Programmable Gate Arrays according to claim 8, wherein said analyzing means further sends a stimulation signal to said high speed serial transceiver.

10. A method for debugging a Field Programmable Gate Array having a logic unit under test, the method comprising:

probing a probe signal of at least one probe point in said logic unit under test;

converting said probe signal into a high speed serial signal and sending it to an external analyzing means; and

analyzing said signal.

11. The method for debugging a Field Programmable Gate Array according to claim 10, further comprising:

inputting a stimulation signal into said Field Programmable Gate Array in a form of a high speed serial signal;

converting said high speed serial stimulation signal into a low speed parallel stimulation signal; and

applying said stimulation signal to said logic unit under test.

12. The method for debugging a Field Programmable Gate Array according to claim 10, wherein said step of analyzing said signal comprises analyzing whether the logic of said logic unit under test is correct based on said signal and said stimulation signal.

13. A computer program embodied in computer readable memory, the computer program comprising:

a probe signal selecting module configured to select at least one probe point from a plurality of probe points in a logic unit under test of a Field Programmable Gate Array, and obtain a probe signal at said probe point; and

a configuration module for enabling a high speed serial transceiver to convert said probe signal into a high speed serial signal and transmit it to outside the Field Programmable Gate Array.

14. The computer program according to claim 13, wherein:

said high speed serial transceiver is configured to also receive a stimulation signal; and

said computer program further comprising;

a load module for loading configuration data into the Field Programmable Gate Array; and

a stimulation signal selecting module configured to select a stimulation signal received by said high speed serial transceiver and apply it to said logic unit under test.

15. A system for configuring a Field Programmable Gate Array, comprising loading configuration data into means in the Field Programmable Gate Array to enable the Field Programmable Gate Array to have following functional modules:

a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in a logic unit under test of said Field Programmable Gate Array, and obtain a probe signal at said probe point; and

a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit it to outside.

16. The system according to claim 15, wherein said high speed serial transceiver also receives a stimulation signal, and said Field Programmable Gate Array further has following functional modules:

a stimulation signal selecting unit configured to select a stimulation signal received by said high speed serial transceiver or a signal of other signal sources and apply it to said logic unit under test.