Semiconductor Devices Having Low Threading Dislocations and Improved Light Extraction and Methods of Making the Same

• US 20080121910A1
• Filed: 11/28/2006
• Published: 05/29/2008
• Est. Priority Date: 11/28/2006
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Hansen, Jason, Bergmann, Michael John, Haberern, Kevin Ward, Emerson, David Todd
• Granted Patent: US 9,318,327 B2
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02392 Phosphides
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02403 Oxides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02425 Conductive materials, e.g. metallic silicides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 31/0236 Special surface textures
• CPC Class Codes: H01L 31/02363 of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

Semiconductor device structures are provided that are suitable for use in the fabrication of electronic devices such as light emitting diodes. The semiconductor device structures include a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon. The device structure can include an epitaxial region having reduced defects and/or improved radiation extraction efficiency on the roughened growth surface of the substrate. The roughened growth surface of the substrate can have an average roughness R_a of at least about 1 nanometer (nm) and an average peak to valley height R_z of at least about 10 nanometers (nm).

Claims

1. A semiconductor device structure suitable for use in the fabrication of electronic devices such as light emitting diodes, comprising:

a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon; and

an epitaxial region on said substrate.

2. The semiconductor device structure of claim 1, wherein the roughened growth surface of the conductive substrate has an average roughness R_a of at least about 1 nanometer (nm).

3. The semiconductor device structure of claim 2, wherein the roughened growth surface of the conductive substrate has an average peak to valley height R_z of at least about 10 nanometers (nm).

4. The semiconductor device structure of claim 1, wherein the epitaxial region includes fewer defects as compared to the same epitaxial region on a substantially smooth growth surface of said substrate.

5. The semiconductor device structure of claim 1, wherein the epitaxial region has a threading dislocation of less than or about 6×

10⁸ cm<sup>−

2</sup>.

6. The semiconductor device structure of claim 5, wherein the epitaxial region has a threading dislocation of less than or about 10⁸ cm⁻

2.

7. The semiconductor device structure of claim 1, wherein the conductive substrate further comprises a second roughened surface opposite the roughened growth surface.

8. The semiconductor device structure of claim 7, wherein the second roughened surface of the conductive substrate has an average roughness R_a of at least about 1 nanometer (nm).

9. The semiconductor device structure of claim 8, wherein the second roughened surface of the conductive substrate has an average peak to valley height R_z of at least about 10 nanometers (nm).

10. The semiconductor device structure of claim 1, wherein said substrate comprises a material selected from silicon carbide, aluminum nitride, gallium nitride, silicon, gallium arsenide, gallium phosphide, zinc oxide, and sapphire.

11. The semiconductor device structure of claim 1, wherein said substrate comprises a conductive substrate.

12. The semiconductor device structure of claim 1, wherein the conductive substrate comprises silicon carbide (SiC).

13. The semiconductor device structure of claim 1, wherein the epitaxial region comprises an active region capable of emitting radiation.

14. The semiconductor device structure of claim 13, wherein the roughened growth surface of the conductive substrate has a roughness sufficient to increase the radiation extraction efficiency of the active region as compared to the radiation extraction efficiency of the same active region on a substantially smooth growth surface.

15. The semiconductor device structure of claim 14, wherein the active region comprises a Group III nitride.

16. The semiconductor device structure of claim 15, wherein the Group III nitride is selected from the group consisting of AlN, GaN, InN, AlGaN, AlInN, InGaN, and AlInGaN.

17. The semiconductor device structure of claim 16, wherein Group III nitride comprises InGaN.

18. The semiconductor device structure of claim 13, further comprising an n-type layer along a first surface of the active region and a p-type layer on a second opposing surface of the active region to form a diode region.

19. The semiconductor device structure of claim 18, wherein each of the n-type layer and the p-type layer comprises a Group III nitride layer.

20. The semiconductor device structure of claim 1, wherein the epitaxial region includes a buffer layer.

21. A light emitting diode, comprising:

a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon; and

a diode region comprising an epitaxial region on the growth surface of the conductive substrate.

22. The light emitting diode of claim 21, wherein the roughened growth surface of the conductive substrate has an average roughness R_a of at least about 1 nanometer (nm).

23. The light emitting diode of claim 22, wherein the roughened growth surface of the conductive substrate has an average peak to valley height R_z of at least about 10 nanometers (nm).

24. The light emitting diode of claim 21, wherein the epitaxial region includes fewer defects as compared to the same epitaxial region on a substantially smooth growth surface of said substrate.

25. The light emitting diode of claim 21, wherein the epitaxial region has a threading dislocation of less than or about 6×

10⁸ cm<sup>−

2</sup>.

26. The light emitting diode of claim 25, wherein the epitaxial region has a threading dislocation of less than or about 10⁸ cm⁻

2.

27. The light emitting diode of claim 21, wherein the substrate further comprises a second roughened surface opposite the roughened growth surface.

28. The light emitting diode of claim 27, wherein the second roughened surface of the substrate has an average roughness R_a of at least about 1 nanometer (nm).

29. The light emitting diode of claim 28, wherein the second roughened surface of the substrate has an average peak to valley height R_z of at least about 10 nanometers (nm).

30. The light emitting diode of claim 21, wherein said substrate comprises a material selected from silicon carbide, aluminum nitride, gallium nitride, silicon, gallium arsenide, gallium phosphide, zinc oxide, and sapphire.

31. The light emitting diode of claim 21, wherein said substrate comprises a conductive substrate.

32. The light emitting diode of claim 21, wherein the substrate comprises silicon carbide (SiC).

33. The light emitting diode of claim 21, wherein the diode region comprises a n-type layer, an active region, and a p-type layer.

34. The light emitting diode of claim 33, wherein each of the n-type layer, the active layer and the p-type layer independently comprises a Group III nitride layer.

35. The light emitting diode of claim 21, further comprising a reflective layer on a surface of the diode region opposite the substrate.

36. The light emitting diode of claim 35, further comprising a submount on a surface of the reflective layer opposite the diode region.

37. The light emitting diode of claim 21, wherein said substrate comprises a conductive substrate and further comprising a first ohmic layer on a surface of the conductive substrate opposite the diode region and a second ohmic contact on a surface of the diode region opposite the conductive substrate.

38. A method of fabricating a semiconductor device structure suitable for use in the fabrication of electronic devices such as light emitting diodes, comprising:

treating a substrate growth surface suitable for supporting the growth of an epitaxial region thereon to roughen the growth surface; and

forming an epitaxial region on the roughened growth surface of the conductive substrate.

39. The method of claim 38, wherein the treating step comprises treating the growth surface of the substrate under conditions sufficient to provide a growth surface having an average roughness R_a of at least about 1 nanometer (nm).

40. The method of claim 39, wherein the treating step comprises treating the growth surface of the substrate under conditions sufficient to provide a growth surface having an average peak to valley height R_z of at least about 10 nanometers (nm).

41. The method of claim 38, wherein the forming step comprises forming an epitaxial region having fewer defects as compared to the same epitaxial region on a substantially smooth growth surface of said substrate.

42. The method of claim 38, wherein the forming step comprises forming an epitaxial region having a threading dislocation of less than or about 6×

10⁸ cm<sup>−

2</sup>.

43. The method of claim 42, wherein the forming step comprises forming an epitaxial region having a threading dislocation of less than or about 10⁸ cm⁻

2.

44. The method of claim 38, further comprising treating a second surface of the substrate opposite the epitaxial layer under conditions sufficient to roughen the second substrate surface.

45. The method of claim 44, wherein the step of treating the second opposing surface of the substrate comprises treating the second surface of the substrate under conditions sufficient to impart thereto an average roughness R_a of at least about 1 nanometer (nm).

46. The method of claim 45, wherein the step of treating the second opposing surface of the substrate comprises treating the second surface of the substrate under conditions sufficient to impart thereto an average peak to valley height R_z of at least about 10 nanometers (nm).

47. The method of claim 38, wherein said substrate comprises a material selected from silicon carbide, aluminum nitride, gallium nitride, silicon, gallium arsenide, gallium phosphide, zinc oxide, and sapphire.

48. The method of claim 38, wherein said substrate comprises a conductive substrate.

49. The method of claim 38, wherein the substrate comprises silicon carbide (SiC).

50. The method of claim 38, wherein the forming step comprising forming an epitaxial region comprising an active region capable of emitting radiation.

51. The method of claim 50, wherein the treating step comprises treating the growth surface under conditions sufficient to provide a growth surface roughness sufficient to increase the radiation extraction efficiency of the active region as compared to the radiation extraction efficiency of the same active region on a substantially smooth growth surface.

52. The method of claim 51, wherein the active region comprises a Group III nitride.

53. The method of claim 52, wherein the Group III nitride is selected from the group consisting of AlN, GaN, InN, AlGaN, AlInN, InGaN, and AlInGaN.

54. The method of claim 53, wherein Group III nitride comprises InGaN.

55. The method of claim 50, further comprising forming an n-type layer along a first surface of the active region and forming a p-type layer on a second opposing surface of the active region to form a diode region.

56. The method of claim 55, wherein each of the n-type layer and the p-type layer comprises a Group III nitride layer.

57. The method of claim 38, wherein the forming step comprises forming an epitaxial buffer layer.

58. The method of claim 38, wherein the treating step comprises mechanically treating the growth surface of the substrate.

59. The method of claim 38, wherein the treating step comprises etching the growth surface of the substrate.

60. The method of claim 38, wherein the treating step comprises photonically treating the growth surface of the substrate.

61. The method of claim 55, further comprising the step of providing a reflective layer on a surface of the diode region opposite the substrate.

62. The method of claim 61, further comprising providing a submount on a surface of the reflective layer opposite the diode region.

63. The method of claim 55, further comprising providing a first ohmic layer on a surface of the substrate opposite the diode region and providing a second ohmic contact on a surface of the diode region opposite the substrate.