Method to generate airgaps with a template first scheme and a self aligned blockout mask

• US 20080122106A1
• Filed: 09/11/2006
• Published: 05/29/2008
• Est. Priority Date: 09/11/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines SA (International Business Machines Corporation)
• Inventors: Poncth, Shom, Purushothaman, Sampath, Edelstein, Daniel C., Colburn, Matthew E., Nitta, Satyanarayana Venkata
• Granted Patent: US 7,863,150 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps

Abstract

A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

Claims

1. A wafer containing an interconnect structure with airgaps comprising:

a) a substrate having at least one dielectric cap layer on the substrate, and at least one interconnect with spaces between the interconnect; and

b) multiple perforations in the cap layer on top of the interconnect and which overlay the spaces between the interconnect,

wherein the perforations are ordered throughout the wafer with no change in order orientation.

2. The structure of claim 1 wherein the perforations are sub-lithographic.

3. The structure of claim 1 wherein the perforations are supra lithographic.

4. The structure of claim 1 wherein the perforations in the cap layer are pinched off with multiple and discrete pinch-points within a given space between the interconnect and having pinch-off heights that are on order of the perforations.

5. The structure of claim 1 wherein the perforations are at least as small as the minimum distance between the interconnect.

6. The structure of claim 1 wherein the perforations are smaller than the minimum distance between the interconnect.

7. The structure of claim 1 wherein perforation size is reduced by silyation.

8. The structure of claim 1 wherein perforation size is reduced by the deposition of a self assembled monolayer.

9. The structure of claim 1 further comprising a resist layer on the cap layer 15 having multiple perforations wherein the perforation size in the resist layer is reduced using chemically assisted shrinks.

10. A method to fabricate a very low effective dielectric constant interconnect structure comprising:

a. depositing at least one layer of dielectric having interconnects with spaces on a substrate;

b. depositing at least one cap layer on the dielectric layer;

c. depositing an antireflective coating layer and a resist layer;

d. applying a lithographic blockout mask with perforations forming a pattern in the space between the interconnects;

e. transferring the perforation pattern into the cap layer;

f. extracting the underlying dielectric layer between the interconnects through the perforated cap layer;

g. depositing an at least second dielectric layer; and

h. pinching-off the perforations with the at least second dielectric layer.

11. The method of claim 10 wherein the interconnect is a copper interconnect.

12. The method of claim 10 wherein the perforations in the blockout mask are sub-lithographic.

13. The method of claim 10 wherein the perforations in the blockout mask are supra-lithographic.

14. The method of claim 10 wherein the perforations are optionally transferred in the dielectric layer using reactive ion etching.

15. The method of claim 10 wherein the depth of the transferred perforations in the dielectric layer exceeds the depth of the interconnect.

16. The method of claim 10 wherein the depth of the transferred perforations in the dielectric layer is at least 25% deeper than the depth of the interconnect.

17. The method of claim 10 wherein the perforations are at least as small as the minimum distance of the spaces between the interconnect.

18. The method of claim 10 wherein the perforations are smaller than the minimum distance of the spaces between the interconnect.

19. The method of claim 10 further comprising reducing the size of the perforations in the resist layer using chemically assisted shrink.

20. The method of claim 10 further comprising:

a) depositing a conformal layer on the cap layer; and

b) etching through the bottom of the conformal layer.

21. The method of claim 20 wherein the conformal layer is about 5 nm to about 25 nm thick.

22. The method of claim 20 wherein the conformal layer is deposited by chemical vapor deposition, atomic layer deposition, spin-on or combinations thereof.

23. The method of claim 10 further comprising:

a) patterning the resist layer; and

b) silylating the resist layer with a silyation agent.

24. The method of claim 23 wherein the silylation agent is a long chain polymeric siloxane.

25. The method of claim 23 wherein the silylation agent is polydimethyl siloxane.

26. The method of claim 10 further comprising depositing a self assembled monolayer on top of the patterned resist layer.

27. The method of claim 26 wherein the self assembled monolayer is a long chain aliphatic compound.

28. The method of claim 26 wherein the self assembled monolayer is a long chain aromatic compound.

29. The method of claim 10 further comprising depositing a second cap deposition prior to the deposition of the at least second dielectric layer.

30. The method of claim 29 wherein the perforations are pinched off by the deposition of the second cap layer.

31. The method of claim 29 wherein the perforations are pinched off by the deposition of the subsequent dielectric layer.

32. A method to fabricate a very low effective dielectric constant interconnect structure comprising:

a. depositing at least one layer of dielectric having interconnects on a substrate;

b. depositing at least one cap layer on the dielectric layer;

c. depositing an imprintable mask layer on the cap layer;

d. applying an imprint pattern with perforations forming a pattern in the dielectric between the interconnects onto the imprintable mask layer;

e. transferring the perforation pattern into the cap layer and optionally, the dielectric layer;

f. extracting the underlying dielectric layer between the interconnects through the perforated cap layer;

g. depositing an at least second dielectric layer; and

h. pinching-off the perforations with the at least second dielectric layer.

33. The method of claim 32 wherein the extracting step is an etching step.

34. The method of claim 33 wherein the etching step includes an etchant selected from the group consisting of vapor based etchant, wet etchant, CO₂ based etchant and combinations thereof.

35. The method of claim 33 wherein the etchant is an acidic etchant.

37. The method of claim 33 wherein the etchant is a basic etchant.

36. The method of clam 35 wherein the etchant is a hydrofluoric based etchant.

38. The method of clam 37 wherein the etchant is an ammonium hydroxide based etchant.